Error when trying to visualize a .vcd

[miquelt9]

Hi,
I am Miquel and I've been trying to obtain a visualization for a trace.vcd file recently. Unfortunately I am encountering the following error "ValueError: A signal (clk) has no ids".
Here are the files I am using: config.json and trace_induct.txt.

For more context I've used the trace that is generated by eqy when comparing gate.v and gold.v since my goal is to connect them.

Note that I've uploaded the files as txt, as Github didn't allow me to upload them with the original extension name.

Thanks in advance,
Miquel

[martonbognar]

Hi Miquel,

When defining the names of the signals, you need to include the Verilog hierarchy in the naming. In your case, this means naming your signal miter.gate.clk instead of simply clk. This is necessary because multiple signals called clk can exist in different scopes. In addition, I found a formatting difference in your generated VCD file compared to ones I've seen before, I'll push a fix for this soon.

[miquelt9]

Hi Marton,

Thanks for your reply, I tried changing the name but I unfortunately still keep getting the same error ("ValueError: A signal (miter.gate.clk) has no ids".) with the fix you pushed. Is there any libraries involved I might not be taking into account?

[martonbognar]

Can you double-check that you're using the correct vcd file? With the one you posted and the following config.json, the trace generation works for me:

{
  "file_path": "./trace_induct.vcd",
  "clk_signal": "miter.gate.clk",
  "signals": [
    {
      "name": "miter.gate.count",
      "color": "red",
      "label": "Counter",
      "type": "hex"
    },
    {
      "name": "miter.gate.rst",
      "color": "orange",
      "label": "Rest",
      "type": "wire"
    }
  ]
}

I use the following command:

$ ./vcdvis.py -cycles 20 latex
Gathered signals...
IDs collected for ./trace_induct.vcd...
Data collected for ./trace_induct.vcd...
\node at (1, 2) {\footnotesize 1};
\node at (3, 2) {\footnotesize 2};

... output continues ...

[miquelt9]

Worked for me now. I was renaming the clock from the gate.v and gold.v files.
Thank you! 😃