attempt to fix AA3000+ DSP3210 tests and demos fail with ReSDMAC #14

mbtaylor1982 · Oct 20, 2024 · 155d766 · 155d766
1 parent 72cd487
commit 155d766
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Showing 5 changed files with 19 additions and 9 deletions.
diff --git a/Quartus/RESDMAC.tcl b/Quartus/RESDMAC.tcl
@@ -208,7 +208,7 @@ if {$make_assignments} {
 	set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to CSX1
 	set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to CSX0
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to _DREQ
-	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IORDY
+	set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to IORDY
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to _BR
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to R_W_IO
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to _AS_IO

diff --git a/RTL/RESDMAC.v b/RTL/RESDMAC.v
@@ -25,7 +25,7 @@ module RESDMAC(
     input tri1 _CS,                     //_SCSI from Fat Garry
     input tri1 _RST,                    //System Reset
     input tri1 _BERR,               	//Bus Error
-    input [6:2] ADDR,              //CPU address Bus, bits are actually [6:2]
+    input [6:2] ADDR,                   //CPU address Bus, bits are actually [6:2]
 
     // Bus Mastering/Arbitration.
     output  tri1 _BR,               //Bus Request
@@ -44,15 +44,15 @@ module RESDMAC(
     output _IOW,                    //Ative Low Write strobe
 
     inout tri1 [15:0] PD_PORT,     	//Peripheral Data port
-	 
+
 	 input INC_ADD,
 	 input IORDY,
 	 input CSX1,
 	 input CSX0,
 	 input INTB,
 	 input JP,
 	 input PIN_D8
-	 
+
 );
 
 reg AS_O_;
@@ -72,7 +72,7 @@ assign  R_W_IO = OWN ? ~DMADIR : 1'bz;
 wire [31:0] DATA_I;
 wire [31:0] DATA_O;
 assign DATA_I = DATA_IO;
-assign DATA_IO = ((R_W & ~H_0C & ~_CS) | OWN) ? DATA_O : 32'hzzzzzzzz;
+assign DATA_IO = ((R_W & ~H_0C & ~H_5C & ~_CS) | OWN) ? DATA_O : 32'hzzzzzzzz;
 
 wire [15:0] PDATA_I;
 wire [15:0] PDATA_O;
@@ -116,6 +116,7 @@ wire FIFOFULL;
 wire FLUSHFIFO;
 wire ACR_WR;
 wire H_0C;
+wire H_5C;
 wire A1;
 wire DMADIR;
 wire DMAENA;
@@ -166,7 +167,6 @@ registers u_registers(
     .RW        (R_W       ),
     .CLK       (CLK45     ),
     .MID       (MID       ),
-    //.STOPFLUSH (STOP_FLUSH_E),
     .STOPFLUSH (STOPFLUSH),
     .RST_      (_RST ),
     .FIFOEMPTY (FIFOEMPTY ),
@@ -177,6 +177,7 @@ registers u_registers(
     .FLUSHFIFO (FLUSHFIFO ),
     .ACR_WR    (ACR_WR    ),
     .h_0C      (H_0C      ),
+    .h_5C      (H_5C      ),
     .A1        (A1        ),
     .INT_O_    (INT_O_    ),
     .DMADIR    (DMADIR    ),
@@ -271,7 +272,6 @@ fifo int_fifo(
     .LLWORD      (LLW       ),
     .LHWORD      (LHW       ),
     .LBYTE_      (LBYTE_    ),
-    //.RST_FIFO_   (DMAENA    ),
     .RST_FIFO_   (RST_FIFO  ),
     .A1          (A1        ),
     .FIFO_ID     (FIFO_ID   ),

diff --git a/RTL/Registers/addr_decoder.v b/RTL/Registers/addr_decoder.v
@@ -8,13 +8,15 @@ module addr_decoder(
   input DMADIR,     // DMADIR from bit from Control Register.
 
   output h_0C,      // RAMSEY ACR Address Decode
+  output h_5C,      // DSP Address Decode
   output WDREGREQ,  // WD33C93  Address Decode
 
   output CONTR_RD_,
   output ISTR_RD_,
   output WTC_RD_,
   output SSPBDAT_RD_,
   output VERSION_RD_,
+  output DSP_RD_,
 
   output CONTR_WR,
   output ACR_WR,
@@ -40,12 +42,14 @@ wire h_20;
 wire h_3C;
 wire h_58;
 
+
+
 wire ADDR_VALID;
 assign ADDR_VALID = ~(DMAC_ | AS_);
 
 assign h_04 = ADDR_VALID & (ADDR == 8'h04);
 assign h_08 = ADDR_VALID & (ADDR == 8'h08);
-assign h_0C = ADDR_VALID & (ADDR == 8'h0C);
+assign h_0C = (ADDR == 8'h0C);
 assign h_10 = ADDR_VALID & (ADDR == 8'h10);
 assign h_14 = ADDR_VALID & (ADDR == 8'h14);
 assign h_18 = ADDR_VALID & (ADDR == 8'h18);
@@ -55,6 +59,7 @@ assign h_20 = ADDR_VALID & (ADDR == 8'h20);
 //assign h_28 = ADDR_VALID & (ADDR == 8'h28);
 //assign h_2C = ADDR_VALID & (ADDR == 8'h2C);
 assign h_3C = ADDR_VALID & (ADDR == 8'h3C);
+assign h_5C = (ADDR == 8'h5C);
 assign h_58 = ADDR_VALID & (ADDR == 8'h58);
 
 assign WDREGREQ = ADDR_VALID & (ADDR[7:4] == 4'h4);
@@ -65,6 +70,7 @@ assign CONTR_RD_    = ~(h_08 & RW);
 assign ISTR_RD_     = ~(h_1C & RW);
 assign SSPBDAT_RD_  = ~(h_58 & RW);
 assign VERSION_RD_  = ~(h_20 & RW);
+assign DSP_RD_      = ~(h_5C & RW);
 
 assign CONTR_WR     = (h_08 & ~RW);
 assign ACR_WR       = (h_0C & ~RW);

diff --git a/RTL/Registers/registers.v b/RTL/Registers/registers.v
@@ -26,6 +26,7 @@ module registers(
   output reg FLUSHFIFO,     //Flush FIFO.
   output ACR_WR,            //input to FIFO_byte_ptr.
   output h_0C,              //input to FIFO_byte_ptr.
+  output h_5C,
   output reg A1,            //Store value of A1 written to ACR.
   output INT_O_,            //INT_2 Output. (maskable by negating INTENA in the control register)
   output DMADIR,            //DMA Direction
@@ -76,6 +77,7 @@ addr_decoder u_addr_decoder(
     .RW             (RW         ),
     .DMADIR         (nDMADIR    ),
     .h_0C           (h_0C       ),
+    .h_5C           (h_5C       ),
     .WDREGREQ       (WDREGREQ   ),
     .WTC_RD_        (WTC_RD_    ),
     .CONTR_RD_      (CONTR_RD_  ),
@@ -128,6 +130,7 @@ registers_term u_registers_term(
     .DMAC_    (DMAC_    ),
     .WDREGREQ (WDREGREQ ),
     .h_0C     (h_0C     ),
+    .h_5C     (h_5C     ),
     .REG_DSK_ (REG_DSK_ )
 );
 

diff --git a/RTL/Registers/registers_term.v b/RTL/Registers/registers_term.v
@@ -6,6 +6,7 @@ module registers_term(
     input DMAC_,
     input WDREGREQ,
     input h_0C,
+    input h_5C,
 
     output reg REG_DSK_
 );
@@ -17,7 +18,7 @@ wire CYCLE_ACTIVE;
 `ifdef COCOTB_SIM
   assign CYCLE_ACTIVE = ~(AS_| DMAC_ | WDREGREQ );
 `else
-  assign CYCLE_ACTIVE = ~(AS_| DMAC_ | WDREGREQ | h_0C);
+  assign CYCLE_ACTIVE = ~(AS_| DMAC_ | WDREGREQ | h_0C | h_5C);
 `endif
 
 always @(posedge CLK or posedge AS_) begin