Removed FLUFHFIFO hack and added it to the CPUFSM + other minor chang…

…es to fix some warnings.
mbtaylor1982 · Oct 20, 2024 · e46df5f · e46df5f
1 parent d3eeb9c
commit e46df5f
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Showing 7 changed files with 37 additions and 40 deletions.
diff --git a/RTL/CPU_SM/CPU_SM.v b/RTL/CPU_SM/CPU_SM.v
@@ -46,7 +46,8 @@ module CPU_SM(
     output reg PLHW,
     output reg PLLW,
     output reg SIZE1,
-    output reg STOPFLUSH
+    output reg STOPFLUSH,
+    output reg RST_FIFO
 );
 
 //clocked inputs
@@ -77,6 +78,7 @@ wire BREQ_d;
 wire BRIDGEIN_d;
 wire INCNI_d;
 wire STOPFLUSH_d;
+wire RST_FIFO_d;
 wire PAS_d;
 wire PDS_d;
 wire PLHW_d;
@@ -126,7 +128,8 @@ CPU_SM_INTERNALS3 u_CPU_SM_INTERNALS (
     .DIEH         (DIEH_d         ),  // output, (wire), 
     .DIEL         (DIEL_d         ),  // output, (wire), 
     .BRIDGEIN     (BRIDGEIN_d     ),  // output, (wire), 
-    .BGACK        (BGACK_d        )   // output, (wire), 
+    .BGACK        (BGACK_d        ),   // output, (wire), 
+    .RST_FIFO     (RST_FIFO_d     )
 );
 
 //clocked reset
@@ -173,6 +176,7 @@ always @(posedge CLK90 or negedge CCRESET_) begin
         PLLW        <= 1'b0;
         SIZE1       <= 1'b0;
         STOPFLUSH   <= 1'b0;
+        RST_FIFO    <= 1'b0;
     end
     else begin
         BGACK       <= BGACK_d;
@@ -193,6 +197,7 @@ always @(posedge CLK90 or negedge CCRESET_) begin
         PLLW        <= PLLW_d;
         SIZE1       <= SIZE1_d;
         STOPFLUSH   <= STOPFLUSH_d;
+        RST_FIFO    <= RST_FIFO_d;
     end
 end
 

diff --git a/RTL/CPU_SM/CPU_SM_INTERNALS3.v b/RTL/CPU_SM/CPU_SM_INTERNALS3.v
@@ -42,7 +42,8 @@ module CPU_SM_INTERNALS3(
     output reg DIEH,        // Data Input Enable for High word.
     output reg DIEL,        // Data Input Enable for Low word.
     output reg BRIDGEIN,    // Send D16-D31 inputs to D0-D15 input lines
-    output reg BGACK        // bus grant acknowledge
+    output reg BGACK,       // bus grant acknowledge
+    output reg RST_FIFO     //Reset for fifo at when flush in write to scsi direction.
 );
 
 //only 27 state are actually used.
@@ -181,12 +182,9 @@ always @(*) begin
         //-- How to keep DMA from reading extra data from CPU on its last FIFO fill?? Beats says its OK if it does
 
         s20: begin
-            casex ({DMAENA, DMADIR, FIFOEMPTY, nDREQ})
-                4'b0xxx     : next_state <= s20;    //DMA is not turned on
-                4'b100x     : next_state <= s20;    //FIFO not empty yet
-                4'b1011     : next_state <= s20;    //Don't put data in FIFO 'til SCSI asks for more
-                4'b1010     : next_state <= s21;    //Time to put data in FIFO
-                4'b11xx     : next_state <= s0;     //go to DMA read mode
+            casex ({DMAENA, DMADIR, FIFOEMPTY, nDREQ, FLUSHFIFO})
+                5'b1010x     : next_state <= s21;    //Time to put data in FIFO
+                5'b11xxx     : next_state <= s0;     //go to DMA read mode
                 default     : next_state <= state;
             endcase
         end
@@ -270,6 +268,7 @@ always @(*) begin
     DIEL        <= 1'b0;
     BRIDGEIN    <= 1'b0;
     BGACK       <= 1'b0;
+    RST_FIFO    <= 1'b0;
 
     case(state)
 
@@ -440,6 +439,12 @@ always @(*) begin
         //-- How to keep DMA from reading extra data from CPU on its last FIFO fill?? Beats says its OK if it does
 
         //s20: no outputs to set for s20
+        s20: begin
+            if (FLUSHFIFO & ~FIFOEMPTY & DMAENA & ~DMADIR & nDREQ)
+                RST_FIFO <= 1'b1;
+            if(FLUSHFIFO & ~FIFOFULL & FIFOEMPTY & DMAENA & ~DMADIR)
+                STOPFLUSH <= 1'b1;
+        end
 
         s21: begin
             BREQ <= 1'b1;

diff --git a/RTL/RESDMAC.v b/RTL/RESDMAC.v
@@ -157,7 +157,7 @@ wire dsack_int;
 wire PD_OE;
 wire INT_O_;
 wire RST_FIFO;
-wire STOP_FLUSH_E;
+wire CPUSM_FIFO_RST;
 
 registers u_registers(
     .ADDR      ({1'b0, ADDR, 2'b00}),
@@ -166,8 +166,8 @@ registers u_registers(
     .RW        (R_W       ),
     .CLK       (CLK45     ),
     .MID       (MID       ),
-    .STOPFLUSH (STOP_FLUSH_E),
-    //.STOPFLUSH (STOPFLUSH),
+    //.STOPFLUSH (STOP_FLUSH_E),
+    .STOPFLUSH (STOPFLUSH),
     .RST_      (_RST ),
     .FIFOEMPTY (FIFOEMPTY ),
     .FIFOFULL  (FIFOFULL  ),
@@ -226,7 +226,8 @@ CPU_SM u_CPU_SM(
     .PLLW          (PLLW        ),
     .PLHW          (PLHW        ),
     .AS_           (AS_I_       ),
-    .BGACK_I_      (_BGACK_I    )
+    .BGACK_I_      (_BGACK_I    ),
+    .RST_FIFO      (CPUSM_FIFO_RST)    
 
 );
 
@@ -370,21 +371,7 @@ assign DSK1_IN_ = _BERR & _DSACK_I[1];
 assign A3 = ADDR[3];
 assign _INT = INT_O_ ? 1'bz : 1'b0;
 
-assign RST_FIFO = (DMAENA & ~(FLUSHFIFO & ~DMADIR));
-
-reg  STOP;
-
-always @(negedge CLK45, negedge _RST)
-begin
-    if (~_RST)
-        STOP <= 0;
-    else if (FLUSHFIFO & ~DMADIR)
-        STOP <= 1;
-end
-
-assign STOP_FLUSH_E = DMADIR ? STOPFLUSH : STOP;
-
-
+assign RST_FIFO = (DMAENA & ~CPUSM_FIFO_RST);
 
 // the "macro" to dump signals
 `ifdef COCOTB_SIM

diff --git a/RTL/Registers/addr_decoder.v b/RTL/Registers/addr_decoder.v
@@ -34,9 +34,9 @@ wire h_14;
 wire h_18;
 wire h_1C;
 wire h_20;
-wire h_24;
-wire h_28;
-wire h_2C;
+//wire h_24;
+//wire h_28;
+//wire h_2C;
 wire h_3C;
 wire h_58;
 
@@ -51,9 +51,9 @@ assign h_14 = ADDR_VALID & (ADDR == 8'h14);
 assign h_18 = ADDR_VALID & (ADDR == 8'h18);
 assign h_1C = ADDR_VALID & (ADDR == 8'h1C);
 assign h_20 = ADDR_VALID & (ADDR == 8'h20);
-assign h_24 = ADDR_VALID & (ADDR == 8'h24);
-assign h_28 = ADDR_VALID & (ADDR == 8'h28);
-assign h_2C = ADDR_VALID & (ADDR == 8'h2C);
+//assign h_24 = ADDR_VALID & (ADDR == 8'h24);
+//assign h_28 = ADDR_VALID & (ADDR == 8'h28);
+//assign h_2C = ADDR_VALID & (ADDR == 8'h2C);
 assign h_3C = ADDR_VALID & (ADDR == 8'h3C);
 assign h_58 = ADDR_VALID & (ADDR == 8'h58);
 

diff --git a/RTL/Registers/registers.v b/RTL/Registers/registers.v
@@ -58,9 +58,9 @@ wire nDMADIR;
 reg [31:0] SSPBDAT;  //Fake Synchronous Serial Peripheral Bus Data Register (used to test SDMAC rev 4 in the test tool by CDH)
 
 reg [8*4:1] VERSION; //used to store the code version (git tag) limited to 4 ascii chars.
-reg [31:0] META_DATA0;
-reg [31:0] META_DATA1;
-reg [31:0] META_DATA2;
+//reg [31:0] META_DATA0;
+//reg [31:0] META_DATA1;
+//reg [31:0] META_DATA2;
 
 
 wire [31:0] WTC;

diff --git a/RTL/Registers/registers_term.v b/RTL/Registers/registers_term.v
@@ -28,8 +28,8 @@ always @(posedge CLK or posedge AS_) begin
   else if (CYCLE_ACTIVE) begin
     if (TERM_COUNTER == 3'd3)
       REG_DSK_ <= 1'b0;
-    if (TERM_COUNTER < 3'd7)
-		TERM_COUNTER <= TERM_COUNTER + 3'b1;
+    else
+		  TERM_COUNTER <= TERM_COUNTER + 3'b1;
   end
 end
 

diff --git a/RTL/datapath/datapath.v b/RTL/datapath/datapath.v
@@ -76,7 +76,7 @@ datapath_input u_datapath_input(
 );
 
 datapath_output u_datapath_output(
-    .CLK        (CLK135     ),
+    .CLK        (CLK        ),
     .DATA       (DATA_O     ),
     .OD         (FIFO_OD    ),
     .MOD        (MOD_TX     ),