added register at 0xDD005C to read DSP status

RTL/RESDMAC.v

@@ -183,7 +183,8 @@ registers u_registers(
     .DMAENA    (DMAENA    ),
     .REG_DSK_  (REG_DSK_  ),
     .WDREGREQ  (WDREGREQ  ),
-    .AS_O      (AS_O_     )
+    .AS_O      (AS_O_     ),
+    .DSP_DATA  (PDATA_I[15:8])
 );
 
 CPU_SM u_CPU_SM(

RTL/Registers/addr_decoder.v

@@ -15,6 +15,7 @@ module addr_decoder(
   output WTC_RD_,
   output SSPBDAT_RD_,
   output VERSION_RD_,
+  output DSP_RD_,
 
   output CONTR_WR,
   output ACR_WR,
@@ -38,8 +39,10 @@ wire h_20;
 //wire h_28;
 //wire h_2C;
 wire h_3C;
+wire h_5C;
 wire h_58;
 
+
 wire ADDR_VALID;
 assign ADDR_VALID = ~(DMAC_ | AS_);
 
@@ -55,6 +58,7 @@ assign h_20 = ADDR_VALID & (ADDR == 8'h20);
 //assign h_28 = ADDR_VALID & (ADDR == 8'h28);
 //assign h_2C = ADDR_VALID & (ADDR == 8'h2C);
 assign h_3C = ADDR_VALID & (ADDR == 8'h3C);
+assign h_5C = ADDR_VALID & (ADDR == 8'h5C);
 assign h_58 = ADDR_VALID & (ADDR == 8'h58);
 
 assign WDREGREQ = ADDR_VALID & (ADDR[7:4] == 4'h4);
@@ -65,6 +69,7 @@ assign CONTR_RD_    = ~(h_08 & RW);
 assign ISTR_RD_     = ~(h_1C & RW);
 assign SSPBDAT_RD_  = ~(h_58 & RW);
 assign VERSION_RD_  = ~(h_20 & RW);
+assign DSP_RD_      = ~(h_5C & RW);
 
 assign CONTR_WR     = (h_08 & ~RW);
 assign ACR_WR       = (h_0C & ~RW);

RTL/Registers/registers.v

@@ -20,6 +20,7 @@ module registers(
   input FIFOFULL,       // FIFO Full Flag
   input INTA_I,         // Interupt input
   input AS_O,           // Address strobe from CPU FSM
+  input DSP_DATA,
 
   output reg [31:0] REG_OD,     //DATA OUT.
   output PRESET,            //Peripheral Reset.
@@ -31,19 +32,21 @@ module registers(
   output DMADIR,            //DMA Direction
   output DMAENA,            //DMA Enabled.
   output REG_DSK_,          //Register Cycle Term.
-  output WDREGREQ           //SCSI IC Chip Select.
+  output WDREGREQ          //SCSI IC Chip Select.
+
 );
 
 wire CONTR_RD_;
 wire CONTR_WR;
 wire ISTR_RD_;
 wire WTC_RD_;
+wire DSP_RD_;
 wire INTENA;
 wire SSPBDAT_RD_;
 wire SSPBDAT_WR;
 wire VERSION_RD_;
 wire VERSION_WR;
-wire [4:0] MuxSelect;
+wire [5:0] MuxSelect;
 
 //Action strobes
 wire ST_DMA;    //Start DMA 
@@ -58,6 +61,7 @@ wire nDMADIR;
 reg [31:0] SSPBDAT;  //Fake Synchronous Serial Peripheral Bus Data Register (used to test SDMAC rev 4 in the test tool by CDH)
 
 reg [8*4:1] VERSION; //used to store the code version (git tag) limited to 4 ascii chars.
+reg [7:0] DSP;
 //reg [31:0] META_DATA0;
 //reg [31:0] META_DATA1;
 //reg [31:0] META_DATA2;
@@ -81,6 +85,7 @@ addr_decoder u_addr_decoder(
     .CONTR_RD_      (CONTR_RD_  ),
     .CONTR_WR       (CONTR_WR   ),
     .ISTR_RD_       (ISTR_RD_   ),
+    .DSP_RD_        (DSP_RD_    ),
     .ACR_WR         (ACR_WR     ),
     .ST_DMA         (ST_DMA     ),
     .SP_DMA         (SP_DMA     ),
@@ -165,13 +170,22 @@ always @(negedge RST_) begin
         VERSION <= "/$V$"; // This will get replaced with the release tag by github eg(v0.4).
 end
 
-assign MuxSelect = {~WTC_RD_, ~ISTR_RD_, ~CONTR_RD_, ~SSPBDAT_RD_, ~VERSION_RD_};
 
-localparam WTC_SEL = 5'b10000;
-localparam ISTR_SEL = 5'b01000;
-localparam CONTR_SEL = 5'b00100;
-localparam SSPBDAT_SEL = 5'b00010;
-localparam VERSION_SEL = 5'b00001;
+always @(negedge CLK or negedge RST_) begin
+    if (~RST_)
+        DSP <= 8'b0;
+    else if (~AS_)
+        DSP <= DSP_DATA;
+end
+
+assign MuxSelect = {~WTC_RD_, ~ISTR_RD_, ~CONTR_RD_, ~SSPBDAT_RD_, ~VERSION_RD_, ~DSP_RD_};
+
+localparam WTC_SEL = 6'b100000;
+localparam ISTR_SEL = 6'b010000;
+localparam CONTR_SEL = 6'b001000;
+localparam SSPBDAT_SEL = 6'b000100;
+localparam VERSION_SEL = 6'b000010;
+localparam DSP_SEL = 6'b000001;
 
 always @(*) begin
     case (MuxSelect)
@@ -180,6 +194,7 @@ always @(*) begin
       CONTR_SEL     : REG_OD <= {23'h0, CNTR_O};
       SSPBDAT_SEL   : REG_OD <= SSPBDAT;
       VERSION_SEL   : REG_OD <= VERSION;
+      DSP_SEL       : REG_OD <= {24'h0, DSP};
       default       : REG_OD <= 32'h00000000;
     endcase
 end