This project introduces a MIPS32 processor with a single-cycle architecture, enabling the execution of any instruction in just one clock cycle. The design, implemented in Verilog, features components like instruction fetch, decode, execute units, a register file, and memory unit. Emphasizing simplicity without compromising performance, the processor demonstrates efficient execution of diverse MIPS instructions in a single clock cycle, serving as a foundational platform for understanding processor architecture and facilitating future enhancements.
