UVM-based Verification Environment for Single Precision FPU

This project entails the development of a comprehensive verification environment for a Single Precision Floating Point Unit (FPU) incorporating fundamental arithmetic operations such as addition, subtraction, multiplication, and division, along with conversions between floating point and integer representations. Leveraging the Universal Verification Methodology (UVM), the verification environment facilitates rigorous testing of the FPU's functionality, ensuring adherence to the IEEE 754 standard for single precision floating point arithmetic.