CP15 Cache Emulation Work #1955

DesperateProgrammer · 2024-01-18T08:53:22Z

The instruction and data cache register were not yet implemented in MelonDS and would act different against the hardware by just reading/writing them.

They have no impact on the - not yet implemented - data cache nor on the instruction cache until their implementation progresses.

JesseTG · 2024-01-18T13:01:25Z

src/ARM.h

@@ -322,6 +322,7 @@ class ARMv5 : public ARM
    u32 RNGSeed;

    u32 DTCMSetting, ITCMSetting;
+    u32 DCacheLockDown, ICacheLockDown;


Don't forget to add these to the savestate (and to increment the savestate version).

JesseTG · 2024-01-18T13:37:35Z

src/CP15.cpp

Thank you. Could you please increment the major version number in Savestate.h as well? It's our only way to detect savestate format changes at runtime; if it's not updated, then loading old states may crash (or worse, silently break the emulated console).

DesperateProgrammer · 2024-01-19T07:22:41Z

I'll add some more changes to the CP15 Caching Instructions and Handling here.

Marked reading CP15 Cache Dirty Bit as not present

DesperateProgrammer · 2024-01-24T08:37:51Z

The last commit was a bit bigger / combined, as adding DCache required other things to not break some applications.

Instruction cache is working except:

Prefetch via CP15 (todo)
CacheLockdown has no effect yet
Timings on cache-fill are not correct yet
Data cache is working except:
Timings on cache fill are not correct yet
Timings on Cache hit are not correct yet
CacheLockdown has no effect yet
WriteBack is not implemented yet (it writes through and invalidates the cache line atm)

CP15 Registers Operations:

Cache Clean has no effect yet (needs write back mechanism)
Cache Clean & Invalidate will now also invalidate the cache (was missing)
Cache Debug Index Register was added
ICache/DCache Tag Registers were added
ICache/DCache Data Registers are not done yet
Privileged/User Checks are missing

… data to get nearer to hw timings

DesperateProgrammer · 2024-01-25T09:21:07Z

Update on the status

Instruction cache is working except:

```
Prefetch via CP15 (todo)
```

Timings on cache-fill are not correct yet

Data cache is working except:

Timings on cache fill are not correct yet

WriteBack is not implemented yet (it writes through)

CP15 Registers Operations:

Cache Clean has no effect yet (needs write back mechanism)

Cache Clean & Invalidate will now also invalidate the cache (was missing)

```
Cache Debug Index Register is working
```

ICache/DCache Tag Registers are working

ICache/DCache Data Registers are working

```
Privileged/User Checks are missing
```

JIT:

Caches are now disabled when JIT is enabled and no longer breaks JIT.

Split the cp15 constants into CP15_Constants.h instead from MemConstants.

Fixed Cache Debug registers were accessible, when op1 != 3 in MCR/MRC instructions Added BIST Test Status register and its cache linefill disable bits

…sent in thumb

Fixed a bug causing overlapping protection regions priority not taken into account, when access permission or cachability bits were changed only on the least priority overlap

Added const properties to the CP15Write/Read functions

Replaced mogic values with named constants Added const specifier to some argument and subsequent calls

Updated documenting comments for the DCacheClear* methods

…ed constant Encapsuled the cache features in #if to disable the features via compile flags

DesperateProgrammer · 2024-02-06T10:18:20Z

This turned out to be quite some rework for the CP15.
The Cache is now working including the write-back mode. Cache Debug registers, BIST Cache Test register
CP15 Registers and Functions received some documenting comments.
Many CP15 related calls received the const-specifier for its arguments when they are not changed in the call.

RSDuck · 2024-02-06T16:30:33Z

src/CP15.cpp


-    id <<= 2;
-    if (ICacheTags[id+0] == tag)
+    for (int set=0;set<ICACHE_SETS;set++)


can you add spaces after the semicolons in all the for loops?

RSDuck · 2024-02-06T16:37:53Z

src/CP15.cpp

+    // Do the same as above but instead of using if-else 
+    // utilize the && and || operators to skip parts of the operations
+    // With the order of comparison we can put the most likely path
+    // checked first


I'm not really sure whether this abusing shortcircuit evaluation really gives better code. If you want to steer the compiler using likely and unlikely markers could be used for the ifs.

I have removed this and added the [[(un)likely]] attributes

RSDuck · 2024-02-06T16:39:15Z

src/CP15.cpp

+    for (int i = 0; i < DCACHE_LINELENGTH; i+=sizeof(u32))
+    {
+        if (tag+i < ITCMSize)
+        {


oh so you can actually put ITCM and DTCM into cache?

I am not entirely sure (I think ) I had a block diagram showing the access passing the write buffer before the TCMs but can't seem to find that diagram. If that is the case, the TCM access will go through the cache when enabled.
However my decision to place the read from TCMs here was to keep the access flow within the line fills in sync to the DataReadXX functions.

RSDuck · 2024-02-06T16:39:47Z

src/CP15.cpp

+                {
+                    if (addr & (DCACHE_LINELENGTH / 2))
+                    {
+                        DCacheTags[id+set] |= CACHE_FLAG_DIRTY_UPPERHALF ;


please remove the spaces before semicolon

RSDuck · 2024-02-06T16:42:57Z

src/CP15.cpp

@@ -306,7 +340,7 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
            MemTimings[i][0] = bustimings[2] << NDS.ARM9ClockShift;
        }

-        if (pu & 0x10)
+        if (pu & CP15_MAP_DCACHEABLE)
        {
            MemTimings[i][1] = kDataCacheTiming;


these values will only ever be used when JIT is enabled, right?

Right now, yes. They are used in ARMv5::CodeRead32, when the JIT is not enabled.

Removed premature optimization and replaced them with [[(un)likely]]

KostaSaizo7 · 2024-04-06T02:13:02Z

Fixes #380

KostaSaizo7 · 2024-04-06T02:18:23Z

Unfortunately #359 is still occuring

Jaklyy · 2024-05-05T11:48:20Z

seems like disabling the pu via the control reg causes melonds to hang under this pr?
at least reproduceable under this test rom:
zboxtesttest.zip

DesperateProgrammer · 2024-05-06T08:08:12Z

Thanks for the report and sample Jakly,

I'll check that as soon i got some time.

Jaklyy · 2024-08-27T23:20:22Z

src/CP15.cpp

-    CodeCycles = (NDS.ARM9MemTimings[addr >> 14][2] + (NDS.ARM9MemTimings[addr >> 14][3] * 7)) << NDS.ARM9ClockShift;
-    CurICacheLine = ptr;
+    //                      first N32                                  remaining S32
+    CodeCycles = (NDS.ARM9MemTimings[tag >> 14][2] + (NDS.ARM9MemTimings[tag >> 14][3] * ((DCACHE_LINELENGTH / 4) - 1))) << NDS.ARM9ClockShift;


minor error: DCACHE_LINELENGTH should be ICACHE_LINELENGTH

DesperateProgrammer and others added 2 commits January 18, 2024 09:39

Added CP15 Data and Instruction Cache Lockdown Register

a2f711c

Merge branch 'melonDS-emu:master' into mem9_timings

3b13cf7

JesseTG reviewed Jan 18, 2024

View reviewed changes

Added ICacheLockDown and DCacheLockDown to CP15 savestate

716b4af

JesseTG reviewed Jan 18, 2024

View reviewed changes

Updated savestate version

a4f8e6f

DesperateProgrammer changed the title ~~CP15 Cache Lockdown Registers~~ CP15 Cache Emulation Work Jan 19, 2024

DesperateProgrammer marked this pull request as draft January 19, 2024 07:21

DesperateProgrammer added 4 commits January 19, 2024 08:30

Cleaned up magic numbers and simplified (not yet used) ICache functions

1019afe

Marked reading CP15 Cache Dirty Bit as not present

Enable instruction cache routines. Fixed typos in constants.

434c234

Replaced more CP15 magic values with named constants

d9fcc2e

Implemented "weird" instruction cache invalidation by Set/Way

b6b0197

DesperateProgrammer force-pushed the mem9_timings branch from b5dedf3 to b6b0197 Compare January 24, 2024 08:48

DesperateProgrammer added 7 commits January 24, 2024 09:51

Implemented DCache and several CP15 registers

0a07661

Added Cache Data Write and Read via CP15

a46f972

Fixed data cache using only 1 cycle on miss.

f67e939

Changed write to cached data from invalidating to updating the cached…

b23cb81

… data to get nearer to hw timings

Fixed unaligned access to data cache

71b5c82

Disabled Caches, when JIT is enabled

7b8327d

Implemented CacheLockDown

9d2e515

DesperateProgrammer and others added 7 commits January 25, 2024 10:24

Merge branch 'melonDS-emu:master' into mem9_timings

028b674

Added CP15 prefetch routine

bf0767b

Removed magic number from Cache Fill timings.

3c94802

Added permission checks to CP15 Cache register write operations

8a0ad8a

Added privilege checks for reading & writing CP15 cache registers

6959d6f

Replaced Magic numbers in CP15 cache type register

cd60c13

Fixed Typo and missing file on the cache type constants

a0f4eb6

DesperateProgrammer and others added 17 commits January 31, 2024 12:20

Cleaned up and fastened up

06ea3f6

Further clean up, removal of magic numbers from CP15.cpp

c8204a8

Split the cp15 constants into CP15_Constants.h instead from MemConstants.

Removed unneccessary wfcsettings file

1a9179b

Added CP15 Trace Process ID

81c9434

Added check of op1 in MCR/MRC

9fa814b

Fixed Cache Debug registers were accessible, when op1 != 3 in MCR/MRC instructions Added BIST Test Status register and its cache linefill disable bits

Included the I/DCache Streaming disable bits in cache lookup

c007540

Added several doxygen-style comments for documentation

02d6fba

Removed Thumb Check on CP15 Access restriction as MCR/MRC are not pre…

f9a831e

…sent in thumb

Cleaned up some more magic numbers

2a385b5

Fixed a bug causing overlapping protection regions priority not taken into account, when access permission or cachability bits were changed only on the least priority overlap

Added more function documenting comments

b1637e2

Added const properties to the CP15Write/Read functions

Added more documenting comments

d5a351a

Added more documenting comments

4b20c1b

Replaced mogic values with named constants Added const specifier to some argument and subsequent calls

Merge branch 'melonDS-emu:master' into mem9_timings

97aabe0

Added write-back ability in addition to write-through for the data cache

129a3e0

Removed some debug remains

a8306f2

Updated documenting comments for the DCacheClear* methods

Fixed an issue with caclulating DTCM/ITCM masks after addr was declar…

4164687

…ed constant Encapsuled the cache features in #if to disable the features via compile flags

Enabled Overlapping region fix again

01bb5f1

DesperateProgrammer marked this pull request as ready for review February 6, 2024 10:18

RSDuck approved these changes Feb 6, 2024

View reviewed changes

Formatting corrections

b2d196c

Removed premature optimization and replaced them with [[(un)likely]]

nadiaholmquist force-pushed the master branch from 10c70eb to a7575ec Compare February 7, 2024 19:21

Merge branch 'melonDS-emu:master' into mem9_timings

9ad2ff3

RSDuck mentioned this pull request Feb 20, 2024

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CP15 Cache Emulation Work #1955

CP15 Cache Emulation Work #1955

DesperateProgrammer commented Jan 18, 2024

JesseTG Jan 18, 2024

JesseTG Jan 18, 2024

DesperateProgrammer commented Jan 19, 2024

DesperateProgrammer commented Jan 24, 2024

DesperateProgrammer commented Jan 25, 2024

DesperateProgrammer commented Feb 6, 2024

RSDuck Feb 6, 2024

RSDuck Feb 6, 2024

DesperateProgrammer Feb 7, 2024

RSDuck Feb 6, 2024

DesperateProgrammer Feb 7, 2024

RSDuck Feb 6, 2024

RSDuck Feb 6, 2024

DesperateProgrammer Feb 7, 2024

KostaSaizo7 commented Apr 6, 2024

KostaSaizo7 commented Apr 6, 2024

Jaklyy commented May 5, 2024

DesperateProgrammer commented May 6, 2024

Jaklyy Aug 27, 2024

CP15 Cache Emulation Work #1955

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CP15 Cache Emulation Work #1955

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