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哈工大《数字电子技术基础》+《数字电子技术基础实验》

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Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
Experiment		Experiment
Homework		Homework
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md

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HIT-DigitalElectronicTechnology

Homework - 大作业
Experiment - 实验
- FPGA1 - FPGA应用1
  - 2fullAdd - 基于74138的双全加器
  - fullAdd - 基于门电路的全加器
  - 4vote - 四人表决电路
  - vFullAdd - 基于Verilog HDL的全加器
  - CheckOddEven - 8位奇偶校验电路
- FPGA2 - FPGA应用2
  - seg7 - 7段显示译码器
  - counter_b - 4位二进制加减计数器
  - fulladd8 - 8位加法器
- design - 自主设计实验

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哈工大《数字电子技术基础》+《数字电子技术基础实验》

digital-electronics harbin-institute-of-technology

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Verilog 100.0%