rv: Return to posedge for the memory

mit-plv · Mar 31, 2020 · df8bb7f · df8bb7f
1 parent c2f78db
commit df8bb7f
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/examples/rv/RVCore.v b/examples/rv/RVCore.v
@@ -420,7 +420,7 @@ Module  RV32ICore.
     Definition T:= struct_t fetch_bookkeeping.
   End FifoFetch.
   Module fromFetch := Fifo1 FifoFetch.
-  Module waitFromFetch := Fifo1Bypass FifoFetch.
+  Module waitFromFetch := Fifo1 FifoFetch.
 
   Module FifoDecode <: Fifo.
     Definition T:= struct_t decode_bookkeeping.

diff --git a/examples/rv/etc/sv/memory.v b/examples/rv/etc/sv/memory.v
@@ -82,7 +82,7 @@ module memory(input  CLK,
    wire put_wf = put_valid && put_ready;
    wire get_wf = get_valid && get_ready;
 
-   always @(negedge CLK) begin
+   always @(posedge CLK) begin
 `ifdef SIMULATION
       if (put_wf && put_request_addr == EXIT_ADDRESS) begin
          if (put_request_data == 0)

diff --git a/examples/rv/rv32.v b/examples/rv/rv32.v
@@ -4,7 +4,7 @@ Require Import RV.RVCore.
 Import RV32ICore.
 
 Definition rv_schedule : scheduler :=
-  Writeback |> Execute |> StepMultiplier |> WaitImem |> Decode |> Fetch |> Imem |> Dmem |> UART_write |> Tick |> done.
+  Writeback |> Execute |> StepMultiplier |> Decode |> WaitImem |> Fetch |> Imem |> Dmem |> UART_write |> Tick |> done.
 
 Definition circuits :=
   compile_scheduler rv_rules rv_external rv_schedule.