Computer System & Architecture Course Project @ GUC
| Tool | Description |
|---|---|
| Java | Programing Language |
| JUnit4 | Testing Suite |
| IntelliJ | IDE for Development |
| Git & Github | Version Control |
- Von Neumann Architecture is a digital computer architecture whose design is based on the concept of stored program computers where program data and instruction data are stored in the same memory.
- The main memory addresses are from 0 to 211 − 1 (0 to 2047).
- Each memory block (row) contains 1 word which is 32 bits (4 bytes).
- The main memory is word addressable.
- Addresses from 0 to 1023 contain the program instructions.
- Addresses from 1024 to 2048 contain the data.
- Size: 32 bits
- 31 General-Purpose Registers (GPRS)
- Names: R1 to R31
- 1 Zero Register
- Name: R0
- Hard-wired value “0” (cannot be overwritten by any instruction).
- 1 Program Counter
- Name: PC
- Instruction Size: 32 bits
- Instruction Types: 3
- R - Type
- I - Type
- J - Type
| R - Type | ||||
|---|---|---|---|---|
| OPCODE | R1 | R2 | R3 | SHAMT |
| 4 | 5 | 5 | 5 | 13 |
| I - Type | |||
|---|---|---|---|
| OPCODE | R1 | R2 | IMMEDIATE |
| 4 | 5 | 5 | 18 |
| J - Type | |
|---|---|
| OPCODE | ADDRESS |
| 4 | 28 |
-
Instructions
Name Mnemonic Type Format Operation Add ADD R ADD R1 R2 R3 R1 = R2 + R3 Subtract SUB R SUB R1 R2 R3 R1 = R2 - R3 Multiply Immediate MULI I MULI R1 R2 IMM R1 = R2 * IMM Add Immediate ADDI I ADDI R1 R2 IMM R1 = R2 + IMM Branch if Not Equal BNE I BNE R1 R2 IMM IF(R1 != R2) {PC = PC+1+IMM } And Immediate ANDI I ANDI R1 R2 IMM R1 = R2 & IMM Or Immediate ORI I ORI R1 R2 IMM R1 = R2 | IMM Jump J J J ADDRESS *PC = PC[31:28] || ADDRESS Shift Left Logical $^∗$ SLL R SLL R1 R2 SHAMT R1 = R2 << SHAMT Shift Right Logical $^∗$ SRL R SRL R1 R2 SHAMT R1 = R2 >>SHAMT Load Word LW I LW R1 R2 IMM R1 = MEM[R2 + IMM] Store Word SW I SW R1 R2 IMM MEM[R2 + IMM] = R1
* || is concatination, SLL and SRL: R3 will be 0 in the instruction format.