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Merge pull request #1 from mrLSD/feat/sipeed-tangnano
Feat: add Sipeed TangNano 9k board
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# FPGA | ||
FPGA samples. Most of them base on Verilog or SystemVerilog. | ||
Implemented for Altera Development Board with Quartus CAD. | ||
# FPGA Research & Development | ||
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## Projects | ||
## Supported boards | ||
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- Altera devboard Cyclone IV E - `EP4CE10E22C8` | ||
- Sipeed TangNano 9k | ||
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## Sipeed TangNano 9k | ||
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- Usefull getting started guides: | ||
- Sipeed [website]() | ||
- [Lushat Labs articles](https://learn.lushaylabs.com/getting-setup-with-the-tang-nano-9k/#creating-a-new-project) | ||
- github examples: | ||
- https://github.com/lushaylabs/tangnano9k-series-examples | ||
- https://github.com/sipeed/TangNano-9K-example | ||
- required: [OSS Cad Suite](https://github.com/YosysHQ/oss-cad-suite-build) or just install [Gowin EDA](https://www.gowinsemi.com/en/support/download_eda/). | ||
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### Altera Devboard | ||
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- Devboard: `Cyclone IV E EP4CE10E22C8` | ||
- Quartus CAD required | ||
FPGA project mostly base on Verilog or SystemVerilog. And implemented for Altera DevelopmentBoard with Quartus CAD. | ||
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#### Altera based projects | ||
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* **VGA** - output via VGA interfact to motinors. Can draw multy line text with specific fonts. | ||
* **led4_highreg** - 12 LED circle sequence | ||
* **timer** - count down timer with ability set timer time. | ||
* **timer** - onboard digital LED count down timer with ability set timer time. | ||
Digital LED and Keys used for I/O. | ||
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### LICENSE MIT |
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BOARD=tangnano9k | ||
FAMILY=GW1N-9C | ||
DEVICE=GW1NR-LV9QN88PC6/I5 | ||
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all: app.fs | ||
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# Synthesis | ||
app.json: top.v lcd.v gowin_rpll/gowin_rpll.v | ||
yosys -p "read_verilog lcd.v top.v gowin_rpll/gowin_rpll.v; synth_gowin -top top -json app.json" | ||
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# Place and Route | ||
app_pnr.json: app.json | ||
nextpnr-gowin --json app.json --write app_pnr.json --freq 27 --device ${DEVICE} --family ${FAMILY} --cst ${BOARD}.cst | ||
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# Generate Bitstream | ||
app.fs: app_pnr.json | ||
gowin_pack -d ${FAMILY} -o app.fs app_pnr.json | ||
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# Program Board | ||
load: app.fs | ||
openFPGALoader -b ${BOARD} app.fs -f | ||
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# Generate Simulation | ||
screen_test.o: app.v app_tb.v | ||
iverilog -o app_test.o -s test app.v app_tb.v | ||
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# Run Simulation | ||
test: app_test.o | ||
vvp app_test.o | ||
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# Cleanup build artifacts | ||
clean: | ||
rm app.vcd app.fs app_test.o | ||
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.PHONY: load clean test | ||
.INTERMEDIATE: app_pnr.json app.json app_test.o |
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