Sha256 refactor #206
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Sha256 refactor #206
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…nt specific use-cases like #205; also implement SSSE3 acceleration (2006, Intel Core 2 Duo)
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This PR updates the SHA256 implementation
cleanly separates message scheduling and hashing round. Message scheduling is independent of previous data and can be parallelized 4x uint32 per 4x uint32. For known padding blocks, such as those that arises in Merkle trees (see Accelerate Merkle tree hashing #205), it can be precomputed for significant speedups.
implements SSSE3 (introduced in 2006, via Core 2 Duo) to parallelize message scheduling. This speeds SHA256 by 30%.
Note: the SIMD rotate instruction
_mm_ror_epi32to trivially translate sha256 was added with AVX512F+AVX512VL.The speedup would only be helpful on Skylake-X as the only architecture with AVX512VL but no hardware SHA (Cannon Lake never shipped). And that speedup would be limited to replacing shifts+xors with rotate
implements hardware SHA acceleration
reduce the size of sha256 context and simplify its update flow
Performance on small messages is greater than OpenSSL and BLST
