Project: Register File + ALU
Milestone Checklist
- Preliminary project cell layouts: defines full schematic hierarchy and functionality.
- updated version of your milestone #2 writeup with any changes based on comments made. [ updated MS#2 submission with errors fixed (Canvas)]
- conclusion is missing.
- drop multiplication for ALU
- schematic is not working
- demonstrate loading of values to the reg file and operating on them
- Please only include one test harness. It should consist of input pins, output ins, and a single part.
- Please turn off the three-state inputs on your input pins
- DFFs have serious design flaws. Please fix Logisim simulation is not working.
- Many of the layouts submitted have design errors in them.
- Please include .cmd files to demonstrate that the layouts simulate proerly
- complete Logisim/LogicWorks schematic (Canvas command)
- .cmd test files for IRSIM (turnin command)
- partially complete set of Magic layouts for standard cells (these should only be submitted if DRC correct) (turnin command)
Magic Hierarchy Development [Layer0 - Layer4]
-- ** *Layer0: transistor-level* **
- magic: OR2 gate
- magic: NOR2 gate
- magic: INV
- magic: OR3 gate
- magic: OR4 gate
- magic: NAND2 gate
- magic: XOR2 gate
- magic: AND2 gate
- magic: AND3 gate
-- ** Layer1: gate-level **
- magic: 1-bit MUX3
- magic: 1-bit MUX2
- magic: 1-bit MUX8
- magic: 1-bit 3-to-8 Decoder
- magic: 1-bit D Flip Flop
- magic: 1-bit full-Adder
- magic: 1-bit full-Subtractor
- magic: 1-bit half-Adder
- magic: 1-bit half-Subtractor
- magic: 4-bit AND2
- magic: 4-bit OR2
- magic: 4-bit NAND2
- magic: 4-bit NOR2
-- ** Layer2: parts-level **
- magic: 4-bit MUX3
- magic: 4-bit MUX8
- magic: 4-bit Register
- magic: 1-bit DFF with Enabler [merge MUX2 + DFF]
- magic: 4-bit Adder
- magic: 4-bit Subtractor
-- ** Layer3: block-level **
- magic: 4-bit Register File
- magic: 4-bit ALU
-- ** Layer4: top-level [single block] **
- magic: 4-bit single-block [merge MUX3 + Register File + ALU]
Progress
- Logisim functional (unless bugs/issues encountered)
- magic gate layouts
- make a single block as top level
- make sure all magic simulates properly (will help us in the long run before we build the parts)
- build MUX3 in magic?
- build Register File in magic?
- build ALU in magic?
Issues
- Fix DFF incorrect output
- Fix Oscillation Apparent
Workload
- Remove Multiplier
- 8 bits to 4 bits
- Remove MUX3?
- cut down number of registers? (8 registers currently)
Abstract: This project shows three crucial blocks: MUX3, Register File, and Arithmetic Logic Unit (ALU). The MUX3 selects data for storage in the Register File, which features 8 registers and dynamic address selection. The ALU performs arithmetic operations based on user selection, producing 4-bit results. Also, the ALU's output loops back to the MUX3, forming a crucial feedback loop for iterative calculations. Understanding these blocks is essential for understanding computing systems.
Parts: MUX3, Reg File, ALU
Top level
4 bit MUX3
1 bit MUX
Register File
MUX8 (to cover 8 registers)
4 bit Register
D Flip Flop + MUX2[as enabler]
D Flip Flop
ALU (Need one more logic to replace multiplier)
