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Processor_design-Resource Utilization by Entity.rpt
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Processor_design-Resource Utilization by Entity.rpt
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Resource Utilization by Entity report for Processor_design
Sun Oct 15 16:38:55 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Resource Utilization by Entity
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------+-------------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------+-------------------+--------------+
; |TopMIPS ; 2590 (0) ; 2206 (0) ; 0 ; 0 ; 0 ; 0 ; 67 ; 0 ; |TopMIPS ; TopMIPS ; work ;
; |DataMemory:dmem| ; 1404 (1404) ; 2048 (2048) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|DataMemory:dmem ; DataMemory ; work ;
; |InsructionMemory2:imem| ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|InsructionMemory2:imem ; InsructionMemory2 ; work ;
; |MIPS:mips| ; 1169 (0) ; 158 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips ; MIPS ; work ;
; |Controller:c| ; 33 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Controller:c ; Controller ; work ;
; |ALUDecoder:ad| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Controller:c|ALUDecoder:ad ; ALUDecoder ; work ;
; |MainDecoder:md| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Controller:c|MainDecoder:md ; MainDecoder ; work ;
; |Datapath:dp| ; 1136 (0) ; 158 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp ; Datapath ; work ;
; |ALU:alu| ; 755 (755) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|ALU:alu ; ALU ; work ;
; |Adder:pcadd1| ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|Adder:pcadd1 ; Adder ; work ;
; |Adder:pcadd2| ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|Adder:pcadd2 ; Adder ; work ;
; |RegisterFile:rf| ; 144 (144) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|RegisterFile:rf ; RegisterFile ; work ;
; |ResetableFF:pcreg| ; 13 (13) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|ResetableFF:pcreg ; ResetableFF ; work ;
; |mux2:jal_resmux| ; 112 (112) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|mux2:jal_resmux ; mux2 ; work ;
; |mux2:pcjrmux| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|mux2:pcjrmux ; mux2 ; work ;
; |mux2:pcmux| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|mux2:pcmux ; mux2 ; work ;
; |mux2:srcbmux| ; 34 (34) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|mux2:srcbmux ; mux2 ; work ;
; |mux4:resmux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TopMIPS|MIPS:mips|Datapath:dp|mux4:resmux ; mux4 ; work ;
+------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------+-------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.