32-Bit-Non-Pipelined-Single-Cycle-Processor

• This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

Processor design and implementation on a FPGA : Project with 3 stages and Stage 1 is the individual project.

Stage 1 (Individual): 32 bit non-pipelined RISC-V processor using Micropramming with 3 bus structure. This is RV32I implementation.

It is required to implement the following classes of instructions:

1. All computational instructions covered by instruction types R and I.
2. All memory access instructions (load and store) - I and S type instructions
3. All Control Flow instructions : SB type