Fix STM32 series defines throughout the code

targets/CMSIS-OS/ChibiOS/Include/targetPAL.h

@@ -9,7 +9,7 @@
 #include <hal.h>
 
 
-#if defined(STM32L0xx_MCUCONF) || defined(STM32F0xx_MCUCONF) || defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF) || defined(STM32H7xx_MCUCONF)
+#if defined(STM32L0XX) || defined(STM32F0XX) || defined(STM32F4XX) || defined(STM32F7XX) || defined(STM32H7XX)
 
 // Contains available GPIO ports for the current board
 extern stm32_gpio_t* gpioPort[];

targets/CMSIS-OS/ChibiOS/common/hard_fault_handler.c

@@ -17,7 +17,7 @@ typedef enum {
     UsageFault = 6,
 } FaultType;
 
-#if defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF)
+#if defined(STM32F4XX) || defined(STM32F7XX)
 
 void NMI_Handler(void) {
     while(1);
@@ -46,7 +46,7 @@ void HardFault_Handler(void) {
     volatile FaultType faultType = (FaultType)__get_IPSR();
 
     // these are not available in all the STM32 series
-#if defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF)
+#if defined(STM32F4XX) || defined(STM32F7XX)
 
     //Flags about hardfault / busfault
     //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
@@ -99,7 +99,7 @@ void UsageFault_Handler(void) {
     (void)faultType;
 
     // these are not available in all the STM32 series
-#if defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF)
+#if defined(STM32F4XX) || defined(STM32F7XX)
 
     //Flags about hardfault / busfault
     //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
@@ -133,7 +133,7 @@ void MemManage_Handler(void) {
     (void)faultType;
 
     // these are not available in all the STM32 series
-#if defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF)
+#if defined(STM32F4XX) || defined(STM32F7XX)
 
     //For HardFault/BusFault this is the address that was accessed causing the error
     volatile uint32_t faultAddress = SCB->MMFAR;

targets/CMSIS-OS/ChibiOS/common/nanoSupport_CRC32.c

@@ -6,9 +6,9 @@
 
 #include <hal.h>
 
-#if defined(STM32F0xx_MCUCONF) || defined(STM32F1xx_MCUCONF) || defined(STM32F2xx_MCUCONF) || \
-	defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF) || defined(STM32L0xx_MCUCONF) || \
-	defined(STM32L1xx_MCUCONF) || defined(STM32H7xx_MCUCONF) 
+#if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F2XX) || \
+	defined(STM32F4XX) || defined(STM32F7XX) || defined(STM32L0XX) || \
+	defined(STM32L1XX) || defined(STM32H7XX) 
 
 // strong implementation of this function specific to the STM32 targets
 unsigned int SUPPORT_ComputeCRC(const void* rgBlock, int nLength, unsigned int crc)

targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp

@@ -105,17 +105,17 @@ void Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::GetI2cConfig(CLR_
     I2cBusSpeed busSpeed = (I2cBusSpeed)managedConfig[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4;
 
     // set the LL I2C configuration (according to I2C driver version)
-    #if defined(STM32F1xx_MCUCONF) || defined(STM32F4xx_MCUCONF) || defined(STM32L1xx_MCUCONF)
+    #if defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32L1XX)
 
     llConfig->op_mode = OPMODE_I2C;
     llConfig->clock_speed = busSpeed == I2cBusSpeed_StandardMode ? 100000U : 400000U;
     llConfig->duty_cycle = busSpeed == I2cBusSpeed_StandardMode ? STD_DUTY_CYCLE : FAST_DUTY_CYCLE_2;
 
     #endif
 
-    #if defined(STM32F7xx_MCUCONF) || defined(STM32F3xx_MCUCONF) || defined(STM32F0xx_MCUCONF) || \
-            defined(STM32L0xx_MCUCONF) ||  defined(STM32L4xx_MCUCONF) || \
-            defined(STM32H7xx_MCUCONF) 
+    #if defined(STM32F7XX) || defined(STM32F3XX) || defined(STM32F0XX) || \
+            defined(STM32L0XX) ||  defined(STM32L4XX) || \
+            defined(STM32H7XX) 
 
     // Standard mode : 100 KHz, Rise time 120 ns, Fall time 25 ns, 54MHz clock source
     // Fast mode : 400 KHz, Rise time 120 ns, Fall time 25 ns, 54MHz clock source
@@ -346,7 +346,7 @@ HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit
             palI2c->Address = (i2caddr_t)connectionSettings[Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings::FIELD___slaveAddress].NumericByRef().s4;
 
             // when using I2Cv1 driver the address needs to be loaded in the I2C driver struct
-    #if defined(STM32F1xx_MCUCONF) || defined(STM32F4xx_MCUCONF) || defined(STM32L1xx_MCUCONF)
+    #if defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32L1XX)
             palI2c->Driver->addr = palI2c->Address;
     #endif
 

targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp

@@ -22,13 +22,13 @@ HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFre
         // Retrieves the needed parameters from private class properties
         double maxFrequency = 0.0;
 
-#if defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF)
+#if defined(STM32F4XX) || defined(STM32F7XX)
         int timerId = (int)(pThis[ FIELD___deviceId ].NumericByRef().u4);
 
         if (timerId == 1 || timerId >= 8) maxFrequency = (double)STM32_PCLK2_MAX;   // TIM1, TIM8 and TIM9 on APB2
         else maxFrequency = (double)STM32_PCLK1_MAX;        // other timers on APB1
 
-#elif defined(STM32F0xx_MCUCONF)
+#elif defined(STM32F0XX)
 
         maxFrequency = (double)STM32_PCLK_MAX;         // Only APB1 on this MCU
 
@@ -54,12 +54,12 @@ HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCou
     NANOCLR_HEADER();
     {
         int pinCount = 0;
-#if defined(STM32F4xx_MCUCONF)
+#if defined(STM32F4XX)
         pinCount = 42;
-#elif defined(STM32F7xx_MCUCONF)
+#elif defined(STM32F7XX)
         //FIXME: arbitrary value, here. Where do I find the information ?
         pinCount = 42;
-#elif defined(STM32F0xx_MCUCONF)
+#elif defined(STM32F0XX)
         pinCount = 24;
 #endif
         stack.SetResult_I4(pinCount);
@@ -132,7 +132,7 @@ HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceS
    #if STM32_PWM_USE_TIM3
        strcat(deviceSelectorString, "TIM3,");
    #endif
-#ifndef STM32F0xx_MCUCONF
+#ifndef STM32F0XX
    #if STM32_PWM_USE_TIM4
        strcat(deviceSelectorString, "TIM4,");
    #endif

targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native.h

@@ -226,7 +226,7 @@ extern uint8_t Uart8_RxBuffer[];
 // the following macro defines a function that initializes an UART struct
 // it gets called in the Windows_Devices_SerialCommunication_SerialDevice::NativeInit function
 
-#if defined(STM32F7xx_MCUCONF) || defined(STM32F0xx_MCUCONF)
+#if defined(STM32F7XX) || defined(STM32F0XX)
 
 // STM32F7 and STM32F0 use UART driver v2
 #define UART_INIT(num, tx_buffer_size, rx_buffer_size) void Init_UART##num() { \

targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp

@@ -140,7 +140,7 @@ uint16_t Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::ComputeBaudRa
     uint16_t divider = 0;
     int32_t maxSpiFrequency;
 
-  #if defined(STM32L0xx_MCUCONF)
+  #if defined(STM32L0XX)
 
     // SP1 is feed by APB2 (STM32_PCLK2)
     actualFrequency = STM32_PCLK2;
@@ -154,7 +154,7 @@ uint16_t Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::ComputeBaudRa
     // from datasheet
     maxSpiFrequency = 12000000;
 
-  #elif defined(STM32F0xx_MCUCONF)
+  #elif defined(STM32F0XX)
 
     (void)busIndex;
 
@@ -164,7 +164,7 @@ uint16_t Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::ComputeBaudRa
     // from datasheet
     maxSpiFrequency = 18000000;
 
-  #elif defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF)
+  #elif defined(STM32F4XX) || defined(STM32F7XX)
 
     // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2)
     actualFrequency = STM32_PCLK2;
@@ -179,7 +179,7 @@ uint16_t Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::ComputeBaudRa
     // because ChibiOS doesn't offer that we have to go with minimum common denominator
     maxSpiFrequency = STM32_SPII2S_MAX;
 
-  #elif defined(STM32H7xx_MCUCONF)
+  #elif defined(STM32H7XX)
 
     // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2)
     actualFrequency = STM32_PCLK2;
@@ -269,10 +269,10 @@ void Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetSPIConfig(int
         if(bufferIs16bits)
         {
             // Set data transfer length to 16 bits
-  #ifdef STM32F4xx_MCUCONF
+  #ifdef STM32F4XX
             llConfig->cr1 |= SPI_CR1_DFF;
   #endif
-  #ifdef STM32F7xx_MCUCONF
+  #ifdef STM32F7XX
             llConfig->cr2 = SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0;
   #endif
             // Sets the order of bytes transmission : MSB first or LSB first
@@ -285,10 +285,10 @@ void Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetSPIConfig(int
         else
         {
             // have to force transfer length to 8bit
-  #ifdef STM32F4xx_MCUCONF
+  #ifdef STM32F4XX
             llConfig->cr1 &= ~SPI_CR1_DFF;
   #endif
-  #ifdef STM32F7xx_MCUCONF
+  #ifdef STM32F7XX
             llConfig->cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0;
   #endif            
         }
@@ -300,21 +300,21 @@ void Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetSPIConfig(int
         if(bufferIs16bits)
         {
             // have to force transfer length to 16bit 
-  #ifdef STM32F4xx_MCUCONF
+  #ifdef STM32F4XX
             llConfig->cr1 |= SPI_CR1_DFF;
   #endif
-  #ifdef STM32F7xx_MCUCONF
+  #ifdef STM32F7XX
             llConfig->cr2 = SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0;
   #endif
 
         }
         else
         {
             // set transfer length to 8bits
-  #ifdef STM32F4xx_MCUCONF
+  #ifdef STM32F4XX
             llConfig->cr1 &= ~SPI_CR1_DFF;
   #endif
-  #ifdef STM32F7xx_MCUCONF
+  #ifdef STM32F7XX
             llConfig->cr2 |= SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0;
   #endif            
         }

targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c

@@ -5,7 +5,7 @@
 
 #include <hal.h>
 
-#if defined(STM32L0xx_MCUCONF) || defined(STM32F0xx_MCUCONF) || defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF) || defined(STM32H7xx_MCUCONF)
+#if defined(STM32L0XX) || defined(STM32F0XX) || defined(STM32F4XX) || defined(STM32F7XX) || defined(STM32H7XX)
 
 stm32_gpio_t* gpioPort[] = { GPIOA, GPIOB
 #if STM32_HAS_GPIOC

targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c

@@ -22,7 +22,7 @@
 ///////////////////////////////////////////////////////////////////////////////
 
 #if (STM32_CRC_PROGRAMMABLE == TRUE) || \
-    defined(STM32F7xx_MCUCONF) || defined(STM32L0xx_MCUCONF) || defined(STM32H7xx_MCUCONF)
+    defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX)
 
 // CRC default configuration.
 static const crcConfig defaultConfig = {
@@ -71,7 +71,7 @@ void crc_lld_start(const crcConfig *config) {
     rccEnableCRC(FALSE);
 
 #if (STM32_CRC_PROGRAMMABLE == TRUE) || \
-    defined(STM32F7xx_MCUCONF) || defined(STM32L0xx_MCUCONF) || defined(STM32H7xx_MCUCONF)
+    defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX)
 
     // set configuration, if supplied
     if (config == NULL)
@@ -88,7 +88,7 @@ void crc_lld_start(const crcConfig *config) {
 #endif
 
 #if (STM32_CRC_PROGRAMMABLE == TRUE) || \
-    defined(STM32F7xx_MCUCONF) || defined(STM32L0xx_MCUCONF) || defined(STM32H7xx_MCUCONF)
+    defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX)
 
     WRITE_REG(CRCD1.Instance->INIT, DEFAULT_CRC_INITVALUE);
 
@@ -141,7 +141,7 @@ uint32_t crc_lld_compute(const void* buffer, int size, uint32_t initialCrc) {
     // get pointer to buffer
     uint8_t* ptr = (uint8_t*)buffer;
 
-#if defined(STM32F1xx_MCUCONF) || defined(STM32L1xx_MCUCONF) || defined(STM32F2xx_MCUCONF) || defined(STM32F4xx_MCUCONF)
+#if defined(STM32F1XX) || defined(STM32L1XX) || defined(STM32F2XX) || defined(STM32F4XX)
     uint32_t size_remainder = 0;
 
     // need to reset CRC peripheral if:
@@ -208,7 +208,8 @@ uint32_t crc_lld_compute(const void* buffer, int size, uint32_t initialCrc) {
         // Reset CRC Calculation Unit
         crc_lld_reset();
 
-  #if (STM32_CRC_PROGRAMMABLE == TRUE)
+  #if (STM32_CRC_PROGRAMMABLE == TRUE) || \
+    defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX)
         // set initial CRC value
         WRITE_REG(CRCD1.Instance->INIT, initialCrc);
   #endif 

targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.h

@@ -59,7 +59,7 @@ typedef struct RNGDriver {
 // From STMicroelectronics Cube HAL 
 /////////////////////////////////////////////////////////////
 
-#if defined(STM32L0xx_MCUCONF)
+#if defined(STM32L0XX)
 // this series uses different names for the buses
 
 #define rccEnableRNG(lp)  rccEnableAPB2(RCC_AHBENR_RNGEN, lp)