zkasm: remove code pertinent to vector and float registers

None of that is available in the zkasm machine.

cranelift/codegen/src/isa/zkasm/abi.rs

@@ -67,15 +67,16 @@ impl ABIMachineSpec for ZkAsmMachineDeps {
     where
         I: IntoIterator<Item = &'a ir::AbiParam>,
     {
+        // FIXME(nagisa): this code needs to be rewritten for zkasm
+        //
         // All registers that can be used as parameters or rets.
         // both start and end are included.
-        let (x_start, x_end, f_start, f_end) = match (call_conv, args_or_rets) {
-            (isa::CallConv::Tail, _) => (10, 11, 0, 0),
-            (_, ArgsOrRets::Args) => (10, 11, 0, 0),
-            (_, ArgsOrRets::Rets) => (10, 11, 0, 0),
+        let (x_start, x_end) = match (call_conv, args_or_rets) {
+            (isa::CallConv::Tail, _) => (10, 11),
+            (_, ArgsOrRets::Args) => (10, 11),
+            (_, ArgsOrRets::Rets) => (10, 11),
         };
         let mut next_x_reg = x_start;
-        let mut next_f_reg = f_start;
         // Stack space.
         let mut next_stack: u32 = 0;
 
@@ -116,10 +117,6 @@ impl ABIMachineSpec for ZkAsmMachineDeps {
                     let x = Some(x_reg(next_x_reg));
                     next_x_reg += 1;
                     x
-                } else if (next_f_reg <= f_end) && *rc == RegClass::Float {
-                    let x = Some(f_reg(next_f_reg));
-                    next_f_reg += 1;
-                    x
                 } else {
                     None
                 };

cranelift/codegen/src/isa/zkasm/inst/emit_tests.rs

@@ -37,20 +37,19 @@ fn test_zkasm_binemit() {
     // TODO: a test with `rets`.
     insns.push(TestUnit::new(
         Inst::Mov {
-            rd: writable_fa0(),
-            rm: fa1(),
-            ty: F32,
+            rd: writable_a0(),
+            rm: b0(),
+            ty: I64,
         },
-        "fa1 => fa0", // FIXME: wrong register names!
+        "B => A",
     ));
-
     insns.push(TestUnit::new(
         Inst::Mov {
-            rd: writable_fa0(),
-            rm: fa1(),
-            ty: F64,
+            rd: writable_a0(),
+            rm: b0(),
+            ty: I32, // FIXME: This *must* zero out the upper 32 bits!
         },
-        "fa1 => fa0", // FIXME: wrong register names!
+        "B => A",
     ));
     // insns.push(TestUnit::new(
     //     Inst::AluRRImm12 {

cranelift/codegen/src/isa/zkasm/inst/regs.rs

@@ -46,28 +46,6 @@ pub fn writable_a2() -> Writable<Reg> {
     Writable::from_reg(a2())
 }
 
-#[inline]
-pub fn fa0() -> Reg {
-    f_reg(10)
-}
-#[inline]
-pub fn writable_fa0() -> Writable<Reg> {
-    Writable::from_reg(fa0())
-}
-#[inline]
-pub fn writable_fa1() -> Writable<Reg> {
-    Writable::from_reg(fa1())
-}
-#[inline]
-pub fn fa1() -> Reg {
-    f_reg(11)
-}
-
-#[inline]
-pub fn fa7() -> Reg {
-    f_reg(17)
-}
-
 /// Get a reference to the zero-register.
 #[inline]
 pub fn zero_reg() -> Reg {
@@ -153,15 +131,7 @@ pub fn create_reg_environment() -> MachineEnv {
             .collect();
 
         let f_registers: Vec<PReg> = Vec::new();
-        // (0..=7)
-        // .chain(10..=17)
-        // .chain(28..=31)
-        // .map(|i| PReg::new(i, RegClass::Float))
-        // .collect();
-
         let v_registers: Vec<PReg> = Vec::new();
-        // (0..=31).map(|i| PReg::new(i, RegClass::Vector)).collect();
-
         [x_registers, f_registers, v_registers]
     };
 
@@ -173,13 +143,7 @@ pub fn create_reg_environment() -> MachineEnv {
         // .collect();
 
         let f_registers: Vec<PReg> = Vec::new();
-        // (8..=9)
-        // .chain(18..=27)
-        // .map(|i| PReg::new(i, RegClass::Float))
-        // .collect();
-
         let v_registers = vec![];
-
         [x_registers, f_registers, v_registers]
     };
 
@@ -201,15 +165,6 @@ pub const fn px_reg(enc: usize) -> PReg {
     PReg::new(enc, RegClass::Int)
 }
 
-#[inline]
-pub fn f_reg(enc: usize) -> Reg {
-    let p_reg = PReg::new(enc, RegClass::Float);
-    let v_reg = VReg::new(p_reg.index(), p_reg.class());
-    Reg::from(v_reg)
-}
-pub const fn pf_reg(enc: usize) -> PReg {
-    PReg::new(enc, RegClass::Float)
-}
 #[inline]
 pub(crate) fn real_reg_to_reg(x: RealReg) -> Reg {
     let v_reg = VReg::new(x.hw_enc() as usize, x.class());
@@ -224,13 +179,3 @@ pub(crate) fn x_reg_range(start: usize, end: usize) -> Vec<Writable<Reg>> {
     }
     regs
 }
-
-#[inline]
-pub fn v_reg(enc: usize) -> Reg {
-    let p_reg = PReg::new(enc, RegClass::Vector);
-    let v_reg = VReg::new(p_reg.index(), p_reg.class());
-    Reg::from(v_reg)
-}
-pub const fn pv_reg(enc: usize) -> PReg {
-    PReg::new(enc, RegClass::Vector)
-}