Merge pull request #101 from near/float_cleanup

Remove float and vector related code
near · Nov 24, 2023 · 557541a · 557541a
2 parents 9b5a612 + 2282d9b
commit 557541a
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Showing 2 changed files with 9 additions and 32 deletions.
diff --git a/cranelift/codegen/src/isa/zkasm/abi.rs b/cranelift/codegen/src/isa/zkasm/abi.rs
@@ -438,7 +438,7 @@ impl ABIMachineSpec for ZkAsmMachineDeps {
                 let r_reg = reg.to_reg();
                 let ty = match r_reg.class() {
                     RegClass::Int => I64,
-                    RegClass::Float => F64,
+                    RegClass::Float => unimplemented!("Float Clobber Saves"),
                     RegClass::Vector => unimplemented!("Vector Clobber Saves"),
                 };
                 insts.push(Self::gen_store_stack(
@@ -465,7 +465,7 @@ impl ABIMachineSpec for ZkAsmMachineDeps {
                 let rreg = reg.to_reg();
                 let ty = match rreg.class() {
                     RegClass::Int => I64,
-                    RegClass::Float => F64,
+                    RegClass::Float => unimplemented!("Float Clobber Restores"),
                     RegClass::Vector => unimplemented!("Vector Clobber Restores"),
                 };
                 insts.push(Self::gen_load_stack(
@@ -572,8 +572,8 @@ impl ABIMachineSpec for ZkAsmMachineDeps {
         // We allocate in terms of 8-byte slots.
         match rc {
             RegClass::Int => 1,
-            RegClass::Float => 1,
-            RegClass::Vector => todo!(),
+            RegClass::Float => unimplemented!("Float number of spillslots"),
+            RegClass::Vector => unimplemented!("Vector number of spillslots"),
         }
     }
 
@@ -657,8 +657,8 @@ fn is_reg_saved_in_prologue(conv: CallConv, reg: RealReg) -> bool {
         // FIXME(#45): Register A for returns? Find where in the code is that defined.
         RegClass::Int if reg.hw_enc() == 10 => false,
         RegClass::Int => true,
-        RegClass::Float => todo!(),
-        RegClass::Vector => todo!(),
+        RegClass::Float => unimplemented!("Float reg saved in prologue"),
+        RegClass::Vector => unimplemented!("Vector reg saved in prologue"),
     }
 }
 

diff --git a/cranelift/codegen/src/isa/zkasm/inst/mod.rs b/cranelift/codegen/src/isa/zkasm/inst/mod.rs
@@ -632,23 +632,7 @@ impl MachInst for Inst {
             F64 => Ok((&[RegClass::Float], &[F64])),
             I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
             _ if ty.is_vector() => {
-                debug_assert!(ty.bits() <= 512);
-
-                // Here we only need to return a SIMD type with the same size as `ty`.
-                // We use these types for spills and reloads, so prefer types with lanes <= 31
-                // since that fits in the immediate field of `vsetivli`.
-                const SIMD_TYPES: [[Type; 1]; 6] = [
-                    [types::I8X2],
-                    [types::I8X4],
-                    [types::I8X8],
-                    [types::I8X16],
-                    [types::I16X16],
-                    [types::I32X16],
-                ];
-                let idx = (ty.bytes().ilog2() - 1) as usize;
-                let ty = &SIMD_TYPES[idx][..];
-
-                Ok((&[RegClass::Vector], ty))
+                unimplemented!("vector register type")
             }
             _ => Err(CodegenError::Unsupported(format!(
                 "Unexpected SSA-value type: {}",
@@ -715,15 +699,8 @@ pub fn reg_name(reg: Reg) -> String {
                 28..=31 => format!("t{}", real.hw_enc() - 25),
                 _ => unreachable!(),
             },
-            RegClass::Float => match real.hw_enc() {
-                0..=7 => format!("ft{}", real.hw_enc() - 0),
-                8..=9 => format!("fs{}", real.hw_enc() - 8),
-                10..=17 => format!("fa{}", real.hw_enc() - 10),
-                18..=27 => format!("fs{}", real.hw_enc() - 16),
-                28..=31 => format!("ft{}", real.hw_enc() - 20),
-                _ => unreachable!(),
-            },
-            RegClass::Vector => format!("v{}", real.hw_enc()),
+            RegClass::Float => unimplemented!("floating register name"),
+            RegClass::Vector => unimplemented!("vector register name"),
         },
         None => {
             format!("{:?}", reg)