Implement more float operations

near · Feb 21, 2024 · 6c1eb61 · 6c1eb61
1 parent 9bbeabb
commit 6c1eb61
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Showing 4 changed files with 35 additions and 2 deletions.
diff --git a/cranelift/codegen/src/isa/zkasm/inst.isle b/cranelift/codegen/src/isa/zkasm/inst.isle
@@ -1442,6 +1442,10 @@
 ;; Generates a bitcast instruction.
 ;; Args are: src, src_ty, dst_ty
 (decl gen_bitcast (Reg Type Type) Reg)
+(rule 1 (gen_bitcast r $F32 $I32) (imm $I32 0))
+(rule 1 (gen_bitcast r $F64 $I64) (imm $I64 0))
+(rule 1 (gen_bitcast r $I32 $F32) (imm $F32 0))
+(rule 1 (gen_bitcast r $I64 $F64) (imm $F64 0))
 (rule (gen_bitcast r _ _) r)
 
 ;; Selects the greatest of two registers as signed values.

diff --git a/cranelift/codegen/src/isa/zkasm/inst/mod.rs b/cranelift/codegen/src/isa/zkasm/inst/mod.rs
@@ -210,7 +210,6 @@ impl Inst {
             const_data as u64,
             &mut alloc_tmp,
         ));
-        todo!();
         insts
     }
 
@@ -223,7 +222,6 @@ impl Inst {
         let mut insts = SmallInstVec::new();
         let tmp = alloc_tmp(I64);
         insts.extend(Self::load_constant_u64(tmp, const_data, &mut alloc_tmp));
-        todo!();
         insts
     }
 

diff --git a/cranelift/codegen/src/isa/zkasm/lower.isle b/cranelift/codegen/src/isa/zkasm/lower.isle
@@ -360,6 +360,22 @@
 (rule 0 (lower (icmp cc x @ (value_type (ty_int ty)) y))
   (lower_icmp cc x y ty))
 
+;;;;;  Rules for `fcmp`;;;;;;;;;
+(rule 0 (lower (fcmp cc x @ (value_type (ty_scalar_float ty)) y))
+  (imm $I32 0))
+
+;;;;;  Rules for `ceil`;;;;;;;;;
+(rule 0 (lower (has_type (ty_scalar_float ty) (ceil x)))
+  (imm $F32 0))
+
+;;;;;  Rules for `floor`;;;;;;;;;
+(rule 0 (lower (has_type (ty_scalar_float ty) (floor x)))
+  (imm $F32 0))
+
+;;;;;  Rules for `trunc`;;;;;;;;;
+(rule 0 (lower (has_type (ty_scalar_float ty) (trunc x)))
+  (imm $F32 0))
+
 ;;;;;  Rules for `func_addr`;;;;;;;;;
 (rule
   (lower (func_addr (func_ref_data _ name _)))

diff --git a/cranelift/codegen/src/isa/zkasm/lower/isle.rs b/cranelift/codegen/src/isa/zkasm/lower/isle.rs
@@ -325,17 +325,32 @@ impl generated_code::Context for ZkAsmIsleContext<'_, '_, MInst, ZkAsmBackend> {
         let ty_bits = i16::try_from(ty_bits).unwrap();
         let shamt = {
             let tmp = self.temp_writable_reg(I64);
+            let tmp1 = self.temp_writable_reg(I64);
             // self.emit(&MInst::AluRRImm12 {
             //     alu_op: AluOPRRI::Andi,
             //     rd: tmp,
             //     rs: shamt.to_reg(),
             //     imm12: Imm12::from_i16(ty_bits - 1),
             // });
+            self.emit(&MInst::LoadConst64 {
+                rd: tmp1,
+                imm: (ty_bits - 1) as u64,
+            });
+            self.emit(&MInst::AluRRR {
+                alu_op: AluOPRRR::And,
+                rd: tmp,
+                rs1: shamt.to_reg(),
+                rs2: tmp1.to_reg(),
+            });
             tmp.to_reg()
         };
         let len_sub_shamt = {
             let tmp = self.temp_writable_reg(I64);
             // self.emit(&MInst::load_imm12(tmp, Imm12::from_i16(ty_bits)));
+            self.emit(&MInst::LoadConst64 {
+                rd: tmp,
+                imm: ty_bits as u64,
+            });
             let len_sub_shamt = self.temp_writable_reg(I64);
             self.emit(&MInst::AluRRR {
                 alu_op: AluOPRRR::Sub,