zkasm hackaton

cranelift/codegen/Cargo.toml

@@ -73,6 +73,7 @@ x86 = []
 arm64 = []
 s390x = []
 riscv64 = []
+zkasm = []
 # Enable the ISA target for the host machine
 host-arch = []
 
@@ -81,7 +82,8 @@ all-arch = [
     "x86",
     "arm64",
     "s390x",
-    "riscv64"
+    "riscv64",
+    "zkasm"
 ]
 
 # For dependent crates that want to serialize some parts of cranelift

cranelift/codegen/build.rs

@@ -33,7 +33,7 @@ fn main() {
         .cloned()
         .filter(|isa| {
             let env_key = format!("CARGO_FEATURE_{}", isa.to_string().to_uppercase());
-            env::var(env_key).is_ok()
+            dbg!(env::var(dbg!(env_key)).is_ok())
         })
         .collect::<Vec<_>>();
 
@@ -200,6 +200,8 @@ fn get_isle_compilations(
 
     let src_isa_risc_v =
         make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("riscv64"));
+    let src_isa_zkasm =
+        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("zkasm"));
     // This is a set of ISLE compilation units.
     //
     // The format of each entry is:
@@ -280,6 +282,17 @@ fn get_isle_compilations(
                 ],
                 untracked_inputs: vec![clif_lower_isle.clone()],
             },
+            IsleCompilation {
+                output: out_dir.join("isle_zkasm.rs"),
+                inputs: vec![
+                    prelude_isle.clone(),
+                    prelude_lower_isle.clone(),
+                    src_isa_zkasm.join("inst.isle"),
+                    src_isa_zkasm.join("inst_vector.isle"),
+                    src_isa_zkasm.join("lower.isle"),
+                ],
+                untracked_inputs: vec![clif_lower_isle.clone()],
+            },
         ],
     })
 }

cranelift/codegen/meta/src/isa/mod.rs

@@ -6,6 +6,7 @@ mod arm64;
 mod riscv64;
 mod s390x;
 pub(crate) mod x86;
+mod zkasm;
 
 /// Represents known ISA target.
 #[derive(PartialEq, Copy, Clone)]
@@ -14,6 +15,7 @@ pub enum Isa {
     Arm64,
     S390x,
     Riscv64,
+    ZkAsm,
 }
 
 impl Isa {
@@ -29,6 +31,7 @@ impl Isa {
     pub fn from_arch(arch: &str) -> Option<Self> {
         match arch {
             "aarch64" => Some(Isa::Arm64),
+            "sparc" | "zkasm" => Some(Isa::ZkAsm),
             "s390x" => Some(Isa::S390x),
             x if ["x86_64", "i386", "i586", "i686"].contains(&x) => Some(Isa::X86),
             "riscv64" | "riscv64gc" | "riscv64imac" => Some(Isa::Riscv64),
@@ -38,7 +41,7 @@ impl Isa {
 
     /// Returns all supported isa targets.
     pub fn all() -> &'static [Isa] {
-        &[Isa::X86, Isa::Arm64, Isa::S390x, Isa::Riscv64]
+        &[Isa::X86, Isa::Arm64, Isa::S390x, Isa::Riscv64, Isa::ZkAsm]
     }
 }
 
@@ -50,6 +53,7 @@ impl fmt::Display for Isa {
             Isa::Arm64 => write!(f, "arm64"),
             Isa::S390x => write!(f, "s390x"),
             Isa::Riscv64 => write!(f, "riscv64"),
+            Isa::ZkAsm => write!(f, "zkasm"),
         }
     }
 }
@@ -61,6 +65,7 @@ pub(crate) fn define(isas: &[Isa]) -> Vec<TargetIsa> {
             Isa::Arm64 => arm64::define(),
             Isa::S390x => s390x::define(),
             Isa::Riscv64 => riscv64::define(),
+            Isa::ZkAsm => zkasm::define(),
         })
         .collect()
 }

cranelift/codegen/meta/src/isa/zkasm.rs

@@ -0,0 +1,101 @@
+use crate::cdsl::isa::TargetIsa;
+use crate::cdsl::settings::SettingGroupBuilder;
+
+macro_rules! define_zvl_ext {
+    (DEF: $settings:expr, $size:expr) => {{
+        let name = concat!("has_zvl", $size, "b");
+        let desc = concat!("has extension Zvl", $size, "b?");
+        let comment = concat!(
+            "Zvl",
+            $size,
+            "b: Vector register has a minimum of ",
+            $size,
+            " bits"
+        );
+        $settings.add_bool(&name, &desc, &comment, false)
+    }};
+    ($settings:expr, $size:expr $(, $implies:expr)*) => {{
+        let has_feature = define_zvl_ext!(DEF: $settings, $size);
+
+        let name = concat!("zvl", $size, "b");
+        let desc = concat!("Has a vector register size of at least ", $size, " bits");
+
+        let preset = $settings.add_preset(&name, &desc, preset!(has_feature $( && $implies )*));
+        (has_feature, preset)
+    }};
+}
+
+pub(crate) fn define() -> TargetIsa {
+    let mut setting = SettingGroupBuilder::new("zkasm");
+
+    let _has_m = setting.add_bool("has_m", "has extension M?", "", false);
+    let _has_a = setting.add_bool("has_a", "has extension A?", "", false);
+    let _has_f = setting.add_bool("has_f", "has extension F?", "", false);
+    let _has_d = setting.add_bool("has_d", "has extension D?", "", false);
+    let _has_v = setting.add_bool("has_v", "has extension V?", "", false);
+    let _has_c = setting.add_bool("has_c", "has extension C?", "", false);
+    let _has_zbkb = setting.add_bool(
+        "has_zbkb",
+        "has extension zbkb?",
+        "Zbkb: Bit-manipulation for Cryptography",
+        false,
+    );
+    let _has_zba = setting.add_bool(
+        "has_zba",
+        "has extension zba?",
+        "Zba: Address Generation",
+        false,
+    );
+    let _has_zbb = setting.add_bool(
+        "has_zbb",
+        "has extension zbb?",
+        "Zbb: Basic bit-manipulation",
+        false,
+    );
+    let _has_zbc = setting.add_bool(
+        "has_zbc",
+        "has extension zbc?",
+        "Zbc: Carry-less multiplication",
+        false,
+    );
+    let _has_zbs = setting.add_bool(
+        "has_zbs",
+        "has extension zbs?",
+        "Zbs: Single-bit instructions",
+        false,
+    );
+
+    let _has_zicsr = setting.add_bool(
+        "has_zicsr",
+        "has extension zicsr?",
+        "Zicsr: Control and Status Register (CSR) Instructions",
+        false,
+    );
+    let _has_zifencei = setting.add_bool(
+        "has_zifencei",
+        "has extension zifencei?",
+        "Zifencei: Instruction-Fetch Fence",
+        false,
+    );
+
+    // Zvl*: Minimum Vector Length Standard Extensions
+    // These extension specifiy the minimum number of bits in a vector register.
+    // Since it is a minimum, Zvl64b implies Zvl32b, Zvl128b implies Zvl64b, etc.
+    // The V extension supports a maximum of 64K bits in a single register.
+    //
+    // See: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#181-zvl-minimum-vector-length-standard-extensions
+    let (_, zvl32b) = define_zvl_ext!(setting, 32);
+    let (_, zvl64b) = define_zvl_ext!(setting, 64, zvl32b);
+    let (_, zvl128b) = define_zvl_ext!(setting, 128, zvl64b);
+    let (_, zvl256b) = define_zvl_ext!(setting, 256, zvl128b);
+    let (_, zvl512b) = define_zvl_ext!(setting, 512, zvl256b);
+    let (_, zvl1024b) = define_zvl_ext!(setting, 1024, zvl512b);
+    let (_, zvl2048b) = define_zvl_ext!(setting, 2048, zvl1024b);
+    let (_, zvl4096b) = define_zvl_ext!(setting, 4096, zvl2048b);
+    let (_, zvl8192b) = define_zvl_ext!(setting, 8192, zvl4096b);
+    let (_, zvl16384b) = define_zvl_ext!(setting, 16384, zvl8192b);
+    let (_, zvl32768b) = define_zvl_ext!(setting, 32768, zvl16384b);
+    let (_, _zvl65536b) = define_zvl_ext!(setting, 65536, zvl32768b);
+
+    TargetIsa::new("zkasm", setting.build())
+}

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -1158,6 +1158,7 @@ impl MachInst for Inst {
     }
 
     fn gen_block_start(
+        _block_index: usize,
         is_indirect_branch_target: bool,
         is_forward_edge_cfi_enabled: bool,
     ) -> Option<Self> {

cranelift/codegen/src/isa/mod.rs

@@ -74,6 +74,9 @@ pub mod riscv64;
 #[cfg(feature = "s390x")]
 mod s390x;
 
+#[cfg(feature = "zkasm")]
+pub mod zkasm;
+
 pub mod unwind;
 
 mod call_conv;
@@ -103,14 +106,15 @@ pub fn lookup(triple: Triple) -> Result<Builder, LookupError> {
         Architecture::Aarch64 { .. } => isa_builder!(aarch64, (feature = "arm64"), triple),
         Architecture::S390x { .. } => isa_builder!(s390x, (feature = "s390x"), triple),
         Architecture::Riscv64 { .. } => isa_builder!(riscv64, (feature = "riscv64"), triple),
+        Architecture::Sparc { .. } => isa_builder!(zkasm, (feature = "zkasm"), triple),
         _ => Err(LookupError::Unsupported),
     }
 }
 
 /// The string names of all the supported, but possibly not enabled, architectures. The elements of
 /// this slice are suitable to be passed to the [lookup_by_name] function to obtain the default
 /// configuration for that architecture.
-pub const ALL_ARCHITECTURES: &[&str] = &["x86_64", "aarch64", "s390x", "riscv64"];
+pub const ALL_ARCHITECTURES: &[&str] = &["x86_64", "aarch64", "s390x", "riscv64", "sparc"];
 
 /// Look for a supported ISA with the given `name`.
 /// Return a builder that can create a corresponding `TargetIsa`.