[WIP] Add WASMI interpreter to benchmarks

Cargo.toml

@@ -216,7 +216,8 @@ byte-array-literals = { path = "crates/wasi-preview1-component-adapter/byte-arra
 
 # Bytecode Alliance maintained dependencies:
 # ---------------------------
-regalloc2 = "0.9.3"
+# regalloc2 = "0.9.3"
+regalloc2 = { path = "/Users/akashin/repos/zk/regalloc2" }
 
 # cap-std family:
 target-lexicon = { version = "0.12.13", default-features = false, features = ["std"] }
@@ -440,4 +441,4 @@ overflow-checks = false
 incremental = false
 debug-assertions = false
 overflow-checks = false
-opt-level = 's'
+opt-level = 's'

cranelift/codegen/src/isa/zkasm/abi.rs

@@ -629,7 +629,7 @@ fn is_reg_saved_in_prologue(conv: CallConv, reg: RealReg) -> bool {
         // FIXME(#45): Register A for returns? Find where in the code is that defined.
         RegClass::Int if reg.hw_enc() == 10 => false,
         RegClass::Int => true,
-        RegClass::Float => unimplemented!("Float reg saved in prologue"),
+        RegClass::Float => false,
         RegClass::Vector => unimplemented!("Vector reg saved in prologue"),
     }
 }

cranelift/codegen/src/isa/zkasm/inst.isle

@@ -314,17 +314,17 @@
   (U16)
   (U32)
   (U64)
-  (Flw)
-  (Fld)
+  (F32)
+  (F64)
 ))
 
 (type StoreOP (enum
   (I8)
   (I16)
   (I32)
   (I64)
-  (Fsw)
-  (Fsd)
+  (F32)
+  (F64)
 ))
 
 (type ZkasmBase (enum
@@ -560,6 +560,52 @@
 (decl temp_writable_xreg () WritableXReg)
 (rule (temp_writable_xreg) (temp_writable_reg $I64))
 
+;; Construct a new `FReg` from a `Reg`.
+;;
+;; Asserts that the register has a Float RegClass.
+(decl freg_new (Reg) FReg)
+(extern constructor freg_new freg_new)
+(convert Reg FReg freg_new)
+
+;; Construct a new `WritableFReg` from a `WritableReg`.
+;;
+;; Asserts that the register has a Float RegClass.
+(decl writable_freg_new (WritableReg) WritableFReg)
+(extern constructor writable_freg_new writable_freg_new)
+(convert WritableReg WritableFReg writable_freg_new)
+
+;; Put a value into a FReg.
+;;
+;; Asserts that the value goes into a FReg.
+(decl put_in_freg (Value) FReg)
+(rule (put_in_freg val) (freg_new (put_in_reg val)))
+(convert Value FReg put_in_freg)
+
+;; Construct an `InstOutput` out of a single FReg register.
+(decl output_freg (FReg) InstOutput)
+(rule (output_freg x) (output_reg x))
+(convert FReg InstOutput output_freg)
+
+;; Convert a `WritableFReg` to an `FReg`.
+(decl pure writable_freg_to_freg (WritableFReg) FReg)
+(extern constructor writable_freg_to_freg writable_freg_to_freg)
+(convert WritableFReg FReg writable_freg_to_freg)
+
+;; Convert a `WritableFReg` to an `WritableReg`.
+(decl pure writable_freg_to_writable_reg (WritableFReg) WritableReg)
+(extern constructor writable_freg_to_writable_reg writable_freg_to_writable_reg)
+(convert WritableFReg WritableReg writable_freg_to_writable_reg)
+
+;; Convert a `WritableFReg` to an `Reg`.
+(decl pure writable_freg_to_reg (WritableFReg) Reg)
+(rule (writable_freg_to_reg x) (writable_freg_to_writable_reg x))
+(convert WritableFReg Reg writable_freg_to_reg)
+
+;; Convert an `FReg` to a `Reg`.
+(decl pure freg_to_reg (FReg) Reg)
+(extern constructor freg_to_reg freg_to_reg)
+(convert FReg Reg freg_to_reg)
+
 ;; Converters
 
 (convert u8 i32 u8_as_i32)
@@ -853,6 +899,10 @@
 (decl imm (Type u64) Reg)
 (extern constructor imm imm)
 
+;; for load immediate float
+(decl fimm (Type u64) Reg)
+(extern constructor fimm fimm)
+
 ;; Imm12 Rules
 
 ; (decl load_imm12 (i32) Reg)
@@ -1236,8 +1286,8 @@
 
 ;; Returns a canonical type for a LoadOP. We only return I64 or F64.
 (decl load_op_reg_type (LoadOP) Type)
-(rule 1 (load_op_reg_type (LoadOP.Fld)) $F64)
-(rule 1 (load_op_reg_type (LoadOP.Flw)) $F64)
+(rule 1 (load_op_reg_type (LoadOP.F64)) $F64)
+(rule 1 (load_op_reg_type (LoadOP.F32)) $F32)
 (rule 0 (load_op_reg_type _) $I64)
 
 ;; helper function to load from memory.
@@ -1442,6 +1492,10 @@
 ;; Generates a bitcast instruction.
 ;; Args are: src, src_ty, dst_ty
 (decl gen_bitcast (Reg Type Type) Reg)
+(rule 1 (gen_bitcast r $F32 $I32) (imm $I32 0))
+(rule 1 (gen_bitcast r $F64 $I64) (imm $I64 0))
+(rule 1 (gen_bitcast r $I32 $F32) (imm $F32 0))
+(rule 1 (gen_bitcast r $I64 $F64) (imm $F64 0))
 (rule (gen_bitcast r _ _) r)
 
 ;; Selects the greatest of two registers as signed values.

cranelift/codegen/src/isa/zkasm/inst/args.rs

@@ -761,14 +761,14 @@ impl LoadOP {
             Self::U16 => "u16",
             Self::U32 => "u32",
             Self::U64 => "u64",
-            Self::Flw => "flw",
-            Self::Fld => "fld",
+            Self::F32 => "f32",
+            Self::F64 => "f64",
         }
     }
 
     pub(crate) fn from_type(t: Type) -> Self {
         if t.is_float() {
-            return if t == F32 { Self::Flw } else { Self::Fld };
+            return if t == F32 { Self::F32 } else { Self::F64 };
         }
         match t {
             R32 => Self::U32,
@@ -786,7 +786,7 @@ impl LoadOP {
             Self::I8 | Self::I16 | Self::I32 | Self::U8 | Self::U16 | Self::U32 | Self::U64 => {
                 0b0000011
             }
-            Self::Flw | Self::Fld => 0b0000111,
+            Self::F32 | Self::F64 => 0b0000111,
         }
     }
     pub(crate) fn funct3(self) -> u32 {
@@ -798,8 +798,8 @@ impl LoadOP {
             Self::U8 => 0b100,
             Self::U16 => 0b101,
             Self::U64 => 0b011,
-            Self::Flw => 0b010,
-            Self::Fld => 0b011,
+            Self::F32 => 0b010,
+            Self::F64 => 0b011,
         }
     }
     pub(crate) fn width(self) -> u32 {
@@ -811,8 +811,10 @@ impl LoadOP {
             Self::U8 => 1,
             Self::U16 => 2,
             Self::U64 => 8,
-            Self::Flw => unimplemented!(),
-            Self::Fld => unimplemented!(),
+            // Self::F32 => unimplemented!(),
+            Self::F32 => 4,
+            // Self::F64 => unimplemented!(),
+            Self::F64 => 8,
         }
     }
 }
@@ -824,13 +826,13 @@ impl StoreOP {
             Self::I16 => "i16",
             Self::I32 => "i32",
             Self::I64 => "i64",
-            Self::Fsw => "fsw",
-            Self::Fsd => "fsd",
+            Self::F32 => "f32",
+            Self::F64 => "f64",
         }
     }
     pub(crate) fn from_type(t: Type) -> Self {
         if t.is_float() {
-            return if t == F32 { Self::Fsw } else { Self::Fsd };
+            return if t == F32 { Self::F32 } else { Self::F64 };
         }
         match t.bits() {
             1 | 8 => Self::I8,
@@ -843,7 +845,7 @@ impl StoreOP {
     pub(crate) fn op_code(self) -> u32 {
         match self {
             Self::I8 | Self::I16 | Self::I32 | Self::I64 => 0b0100011,
-            Self::Fsw | Self::Fsd => 0b0100111,
+            Self::F32 | Self::F64 => 0b0100111,
         }
     }
     pub(crate) fn funct3(self) -> u32 {
@@ -852,8 +854,8 @@ impl StoreOP {
             Self::I16 => 0b001,
             Self::I32 => 0b010,
             Self::I64 => 0b011,
-            Self::Fsw => 0b010,
-            Self::Fsd => 0b011,
+            Self::F32 => 0b010,
+            Self::F64 => 0b011,
         }
     }
     pub(crate) fn width(self) -> u32 {
@@ -862,8 +864,10 @@ impl StoreOP {
             Self::I16 => 2,
             Self::I32 => 4,
             Self::I64 => 8,
-            Self::Fsw => unimplemented!(),
-            Self::Fsd => unimplemented!(),
+            // Self::F32 => unimplemented!(),
+            // Self::F64 => unimplemented!(),
+            Self::F32 => 4,
+            Self::F64 => 8,
         }
     }
 }

cranelift/codegen/src/isa/zkasm/inst/emit.rs

@@ -1617,7 +1617,7 @@ impl MachInstEmit for Inst {
                 ref name,
                 offset,
             } => {
-                unimplemented!("LoadExtName: {name:?}");
+                // unimplemented!("LoadExtName: {name:?}, {offset}");
             }
             &Inst::TrapIfC {
                 rs1,

cranelift/codegen/src/isa/zkasm/inst/emit_tests.rs

@@ -717,21 +717,21 @@ fn test_zkasm_binemit() {
     // insns.push(TestUnit::new(
     //     Inst::Store {
     //         to: AMode::SPOffset(100, I64),
-    //         op: StoreOP::Fsw,
+    //         op: StoreOP::F32,
     //         flags: MemFlags::new(),
     //         src: fa0(),
     //     },
-    //     "fsw fa0,100(sp)",
+    //     "f32 fa0,100(sp)",
     //     0x6a12227,
     // ));
     // insns.push(TestUnit::new(
     //     Inst::Store {
     //         to: AMode::SPOffset(100, I64),
-    //         op: StoreOP::Fsd,
+    //         op: StoreOP::F64,
     //         flags: MemFlags::new(),
     //         src: fa0(),
     //     },
-    //     "fsd fa0,100(sp)",
+    //     "f64 fa0,100(sp)",
     //     0x6a13227,
     // ));
     // insns.push(TestUnit::new(

cranelift/codegen/src/isa/zkasm/inst/mod.rs

@@ -210,7 +210,6 @@ impl Inst {
             const_data as u64,
             &mut alloc_tmp,
         ));
-        todo!();
         insts
     }
 
@@ -223,7 +222,6 @@ impl Inst {
         let mut insts = SmallInstVec::new();
         let tmp = alloc_tmp(I64);
         insts.extend(Self::load_constant_u64(tmp, const_data, &mut alloc_tmp));
-        todo!();
         insts
     }
 
@@ -692,7 +690,7 @@ impl MachInst for Inst {
 
     fn worst_case_size() -> CodeOffset {
         // calculate by test function zkasm_worst_case_instruction_size()
-        1_155
+        12_281
     }
 
     fn ref_type_regclass(_settings: &settings::Flags) -> RegClass {
@@ -742,7 +740,8 @@ pub fn reg_name(reg: Reg) -> String {
                 28..=31 => format!("t{}", real.hw_enc() - 25),
                 _ => unreachable!(),
             },
-            RegClass::Float => unimplemented!("floating register name"),
+            // RegClass::Float => unimplemented!("floating register name"),
+            RegClass::Float => "FLOAT".into(),
             RegClass::Vector => unimplemented!("vector register name"),
         },
         None => {
@@ -964,21 +963,11 @@ impl Inst {
             }
             &Inst::LoadConst32 { rd, imm } => {
                 let rd = format_reg(rd.to_reg(), allocs);
-                let mut buf = String::new();
-                write!(&mut buf, "auipc {},0; ", rd).unwrap();
-                write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
-                write!(&mut buf, "j {}; ", Inst::INSTRUCTION_SIZE + 4).unwrap();
-                write!(&mut buf, ".4byte 0x{:x}", imm).unwrap();
-                buf
+                format!("{} => {}  ;; LoadConst32", imm, rd)
             }
             &Inst::LoadConst64 { rd, imm } => {
                 let rd = format_reg(rd.to_reg(), allocs);
-                let mut buf = String::new();
-                write!(&mut buf, "auipc {},0; ", rd).unwrap();
-                write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
-                write!(&mut buf, "j {}; ", Inst::INSTRUCTION_SIZE + 8).unwrap();
-                write!(&mut buf, ".8byte 0x{:x}", imm).unwrap();
-                buf
+                format!("{} => {}  ;; LoadConst64", imm, rd)
             }
             &Inst::AluRRR {
                 alu_op,
@@ -1064,7 +1053,7 @@ impl Inst {
             } => {
                 let base = from.to_string_with_alloc(allocs);
                 let rd = format_reg(rd.to_reg(), allocs);
-                format!("{} {},{}", op.op_name(), rd, base,)
+                format!("MLOAD {} {},{}", op.op_name(), rd, base,)
             }
             &Inst::Store {
                 to,
@@ -1074,7 +1063,7 @@ impl Inst {
             } => {
                 let base = to.to_string_with_alloc(allocs);
                 let src = format_reg(src, allocs);
-                format!("{} {},{}", op.op_name(), src, base,)
+                format!("MSTORE {} {},{}", op.op_name(), src, base,)
             }
             &Inst::Args { ref args } => {
                 let mut s = "args".to_string();

cranelift/codegen/src/isa/zkasm/inst/regs.rs

@@ -136,7 +136,7 @@ pub fn create_reg_environment() -> MachineEnv {
             .map(|i| PReg::new(i, RegClass::Int))
             .collect();
 
-        let f_registers: Vec<PReg> = Vec::new();
+        let f_registers: Vec<PReg> = (21..=21).map(|i| PReg::new(i, RegClass::Float)).collect();
         let v_registers: Vec<PReg> = Vec::new();
         [x_registers, f_registers, v_registers]
     };