Feature/cgo25 #2
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This let us keep our original switching logic, but we need the arbiter on the first input to always grant the input_pc_and_cc_id: this is needed because we are artificially granting it using the ready signal of the first fifo, hence we do not have any way to stall it. This was done to avoid a deadlock on the switch not sending a valid signal until it receives a ready signal, and the arbiter not sending a ready signal until it receives a valid signal - hence we had a deadlock.
1. Python script that generates a CSV {input, regex_file_path, result}
2. New testbench that reads the CSV and runs the tests
3. Fixed vectorial engine range of a signal
4. Removed check in coprocessor_top (should not be needed?)
Filter protomata regexes valid for compiler regex specification Compile all those regexes with Py and C++ compilers Compare code sizes
1. measuring compile time and compile size of each benchmark/compiler 2. dividing Brill benchmark input 3. Filtering and transforming regexes from the Brill benchmark 4. Scalable way to execute benchmark on board
BRAM read port and CACHE_BLOCK_WIDTH needed to be adjusted to fit CC_ID_BITS > 3
Added instruction for development (+ testing + deployment + benchmarking) Fixed driver to accomodate CC_ID_BITS up to 32 Moved script to start synthesis and added script to extract bitstreams
1. Updated README files 2. Added script to automatically download and preprocess benchmarks 3. Add in-tree downloaded and preprocessed benchmarks, for convenience
This is useful to automate running the different benchmarks in different steps
Provide some pre-made configurations for all test_top.py configurations Then, add a script that runs the benchmark applying a new configuration each time
Automatic aggregation script to reproduce results of paper
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