Implement atomic instructions(A Standard Extension)

[mohanson]

• Update CI with A Extension testsuite
• ckb_vm::run and examples/ckb-vm-runner adds ISA_A by default

[xxuejie]

I noticed a line in RISC-V's spec:

For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2

Does this mean we need to clear the upper 32 bits of rs2 here for all AMO*.W operations?

[mohanson]

After add TEMP1, RS2r, we write the result to memory using the following statement:

mov RS2rd, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_MEMORY(MACHINE, RS1)

It has no affects the final result whether or not the upper 32 bits of rs2 are cleared.

[xxuejie]

2 things:

• The spec requires rd to be sign-extended, which means mov RS2rd might not be correct here?
• For add you are correct, this might end up in the same result, but what about MIN/MAX? Ignoring upper 32 bits or sign-extending can lead to different result, correct?

[mohanson]

• mov RS2rd, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_MEMORY(MACHINE, RS1) moves RS2rd to memory, not rd, and rd = sign_ext(memory[rs1])
• Good question, I need to take a closer look.

[xxuejie]

One more thing: it seems the new issues we found here are not covered by riscv-tests, any chance we can add some unit tests covering checks on those behavior?

[mohanson]

One more thing: it seems the new issues we found here are not covered by riscv-tests, any chance we can add some unit tests covering checks on those behavior?

Yes, I'm going to create some PRs to riscv-tests, but before that I will add tests for ckb-vm.