Rework Build System #7
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Most of the changes are documented in the makefile itself. top.v was renamed so we could use a pattern rule for it. This is further documented in the makefile.
This allows us to use the correct port file via an implicit rule. They both need to be named using the same prefix as the .bin file. There doesn't seem to be a way around this.
Most of the functionality in each project is the same. We can get away with some pattern rules and modifying a few variables in each subproject.
Most of the other projects have only 8k pinmaps
Previously you could only build from the base directory. Now we just run make on the top-level makefile if a sub-makefile gets used directly.
yosys and arachne-pnr are SUPER verbose by default. This should help keep terminal spam to a minimum.
Unfortunately, there is no easy way to reference this, so we're stuck with an ugly include line in every makefile...
Forgot to do this before pushing (whoops)
A few of these projects have been removed for being hard to port (depending on a specific piece of hardware). The fms one has been removed for being not very useful.
The old system only worked for a few boards, using package as a proxy Now we can add support for many more boards just by writing up some pcfs
This allows us to save config options like the BOARD used
Easy to create a script to do any custom flash job
This is roughly from http://zipcpu.com/tutorial/lsn-01-wires.pdf Very useful for testing
If we do `BUTS :=` that means there are *no* buttons. You can test for this with ifdef in your verilog
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This patchset completely reworks the build system to be more idiomatic, and to reduce redundancy. Major changes include:
I have tried to document the top-level makefile fairly heavily, but I've left the sub-makefiles mostly undocumented, due to their duplication. Please let me know if there's anything I can explain, or any changes you would like to know more about.