197x-8080-processor

Inspriation

• Intel 8080
• Intel 8088 (IBM PC)
• MOS Technology 6502 (Apple II)
• Motorola 68000 (Apple Macintosh)

Application Area

Intel 8088 - Nathaniel G.

The Intel 8088 is a general purpose processor, used most notably in the IBM general use PC. It has an 8-bit external data bus, with a 16-bit registers and one megabyte address range.

MOS Tech 6502 - Keenan R.

General use. The MOS Tech 6520 was used in a variety of products such as the original Nintendo Entertainment System to a computer used by the BBC.

Motorola 68000 - Nate W.

The Motorola 68000 was one of the first general-purpose processors with a 32-bit instruction set. It was used in the Apple Macintosh for general computing.

Processor Use

Intel 8088

Sources for table:

• cpuworld
• stackoverflow

Name	Number	Type	Use
AX		Accumulator	Arithmetic, logic, data transfer
BX		Base	Can be used as a 16-bit offset address. Paired by default with segment register "DS." (memory ref. [BX] means [DS:BX]
CX		Counter	Used to control looping
DX		Data	Often used to hold single-byte character data and is referenced as DH or DL. Combines with AX to form a 32-bit register for some operations (e.g. multiply)
CS		Code Segment	Holds
SI		Source Index	Used for pointer addressing, a source in string instructions, offset address relative to DS
DI		Destination Index	Pointer addressing, destination in string processing as ES:DI, offset relative to DS outside of string instructions
BP		Base Pointer	Primarily for accessing parameters and locals on the stack
SP		Stack Pointer	Points to the top item on the stack, address relative to SS (but not for 16-bit addressing), should point to a word, and an empty stack will have SP = FFFEh
CS		Current	Points to current program
DS		Definition	Points to variable definitions
ES		Extra	User defined usage
SS		Stack	points to the stack segment
IP		Instruction Pointer	Always points to the next instruction to be executed. Offset relative to CS
CF,PF,AF,ZF,SF,TF,IF,DF,OF		Flags Register	Determines the current state of the processor.

MOS Tech 6502

Name	Number	Use
A		Accumulator
Y		Index Register
X		Index Register
PC		Program Counter
S		Stack Pointer
P		Processor Status Register

Motorola 68000

Name	Number	Use
D0-D7	1-8	Data Registers
A0-A6	9-15	Address Registers
A7 (USP)	16	Stack Pointer (user)
A7' (SSP)	17	Stack Pointer (supervisor)
PC	18	Program counter
CCR	19	Condition Code Register

Processor OPCodes

Intel 8088

Instruction	Meaning	Notes	Opcode
ADD	add	r/m += r/imm; r += m/imm;	0x00...0x05, 0x80/2...0x83/2
AND	logical AND	r/m &= r/imm; r&= m/imm;	0x20...0x25, 0x80/4...0x83/4
SUB	subtraction	r/m -= r/imm; r-= m/imm;	0x28...0x2D, 0x80...0x83/5
PUSH	Push data onto the stack	*--SP = r/m;	0x06, 0x0E, 0x16, 0x1E, 0x50...0x57, 0x68, 0x6A, 0xFF/6

MOS Tech 6502

Opcode	Operation	Syntax
AND	A AND M -> A	And (IND, X)
ASL	C <-[76543210]<-0	ASL A
BCC	branch on C = 1	BCC oper
DEX	X-1 -> X	DEC

Motorola 68000

Opcode	Operation	Syntax
ADD	Source + Destination -> Destination	Add <ea>,Dn
DIVS	Destination/Source -> Destination	DIVS.W<ea>,Dn
EOR	Source OR Destination -> Destination	EOR Dn,<ea>
MOVEA	Source -> Destination	MOVEAE<ea>,An

Block Diagram

Intel 8088

Datapath

Memory Types

The 8080 contains registers and data segments, which are contained in the Bus Interface Unit, as well as what looks like a queue to contain the next four instructions in the Instruction Stream Byte Queue.

How the ALU and Registers Connect

The ALU is connected to the registers through the A-BUS, which appears to also connect it to the flags and the Bus Interface Unit.

Instruction Implementation

Instructions seem to be stored in the Bus Interface Unit, which includes the Instruction Pointer. Then, the instructions are fed into the ISBQ via the C-BUS before being sent into the Execution Unit Control System.

Processor Pipeline

It seems like the processor does pipeline instructions by using the B-BUS and C-BUS to transmit instructions and information through .

Clock Speed

The 8088 has a clock speed of 5-10MHz.

MOS Tech 6502

Memory Types

The Mos Tech 6502 has several 8-bit registers, including an accumulator register that stores the resluts of arithmetic and logic operations as well as having 2 8-bit general purpose registers.

How the ALU and Registers Connect

The ALU is connected to the registers via the internal data bus

Instruction Implementation

56 Instructions.

Processor Pipeline

The processor status register contains several status flags that are either controlled by the program or the CPU

Clock Speed

The MOS TECH 6502 came in 1,2, and 3 MHz

Motorola 68000

Memory Types

The 68000 contains 32-bit registers and a 32-bit internal data bus. It also has a non-segmented 24-bit address bus.

How the ALU and Registers Connect

The ALU is connected to the registers by the Internal Data Bus.

Instruction Implementation

Instructions seem to be stored in the Cache Holding Register, before being fed down the Instruction Pipe to the Sequencer and Control.

Processor Pipeline

The processor explicitly pipelines instructions, as outlined in the diagram.

Clock Speed

The 68000's clock speed is 4-8 MHz.

Slightly Esoteric Assembly Language

Just another SEA-language

General Purpose 16-Bit Processor

Registers

Reg	Hex	Name	Description
R0-R31	0x00-0x1F	I0-I31	Instruction registers
R0-R7	0x20-0x28	A0-A7	General purpose registers
R8-R15	0x28-0x2A	B0-B7	General purpose registers
R16-R23	0x30-0x37	C0-C7	General purpose registers
R24-R31	0x38-0x3F	D0-D7	General purpose registers

Instruction Set

Instr	Opcode	Description
ADD	0x00	dst <= src + tgt
SUB	0x01	dst <= src - tgt
AND	0x03	dst <= src AND tgt
OR	0x04	dst <= src OR tgt
XOR	0x05	dst <= src XOR tgt
SRR	0x06	dst <= src SRR tgt
SRL	0x07	dst <= src SRL tgt
SLT	0x08	dst <= src SLT tgt
SEQ	0x09	dst <= src SEQ tgt
COPY	0x0A	dst <= src
ADDI	0xFF	dst <= dst + imm
SUBI	0xFE	dst <= dst - imm
COPI	0xFD	dst <= imm
JUMP	0xE0	jump to imm
TJMP	0xFC	jump to imm if dst == 1
FJMP	0xFB	jump to imm if dst == 0

ALU Operations

Opcode	Description
0x00	y <= a + b
0x01	y <= a - b
0x03	y <= a AND b
0x04	y <= a OR b
0x05	y <= a XOR b
0x06	y <= a r_shift b
0x07	y <= a l_shift b
0x08	y <= a SLT b
0x09	y <= a SEQ b

Control Unit States

State	Control Signal Location
mem0WEn	controls(28)
reg0WEn	controls(27)
alu0WEn	controls(26)
aludbufWEn	controls(25)
pcWEn	controls(24)
memibufWEn	controls(23)
memdbufWEn	controls(22);
regR0dbufWEn	controls(21);
regR1dbufWEn	controls(20);
muxPCSel	controls(19);
muxMemASel	controls(18);
muxMemWSel	controls(17);
muxRegA0Sel	controls(16);
muxRegA1Sel	controls(15);
muxRegAWSel	controls(14);
muxRegWDSel	controls(13 downto 12);
muxAluASel	controls(11 downto 10);
muxAluBSel	controls(9 downto 8);
flagOffset	controls(7 downto 4);
aluOp	controls(3 downto 0);

Control Signals

Signal	Location	Description
fetch	"000" & "001000" & "0" & "00" & "00000" & "0000" & "0000" & "0000"	Get instruction
decode	"000" & "000000" & "0" & "00" & "00000" & "0000" & "0000" & "0000"	Decode instruction
getab	"000" & "000011" & "0" & "00" & "00000" & "0000" & "0000" & "0000"	Retrieve A and B from register
geta	"000" & "000010" & "0" & "00" & "10000" & "0000" & "0000" & "0000"	Retrieve A from register
add	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "0000"	aluop for a + b
sub	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "0001"	aluop for a - b
andst	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "0011"	aluop for a AND b
orst	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "0100"	aluop for a OR b
xorst	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "0101"	aluop for a XOR b
srrst	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "0110"	aluop for a SRR b
srlst	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "0111"	aluop for a SRL b
sltst	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "1000"	aluop for a SLT b
seqst	"000" & "100000" & "0" & "00" & "00000" & "0000" & "0000" & "1001"	aluop for a SEQ b
addi	"000" & "100000" & "0" & "00" & "10000" & "0001" & "0000" & "0000"	aluop for a + imm
subi	"000" & "100000" & "0" & "00" & "10000" & "0001" & "0000" & "0001"	aluop for a - imm
copy	"010" & "000000" & "0" & "00" & "00010" & "0000" & "0000" & "0000"	aluop for a SEQ b
copi	"010" & "000000" & "0" & "00" & "00011" & "0000" & "0000" & "0000"	aluop for a SEQ b
jump	"000" & "010000" & "1" & "00" & "00000" & "0000" & "0000" & "0000"	jump to imm
tjmp	"000" & "010000" & regr0bottombit & "00" & "00000" & "0000" & "0000" & "0000"	jump to imm if the last bit of the retrieved register is 1
fjmp	"000" & "010000" & inverseBottomBit & "00" & "00000" & "0000" & "0000" & "0000"	jump to imm if the last bit of the retrieved register is 0
alu_reg	"010" & "000000" & "0" & "00" & "00001" & "0000" & "0000" & "0000"	store result in the alu to the regsiter
pcinc	"000" & "100000" & "0" & "00" & "00000" & "1010" & "0000" & "0000"	send the pc into the alu, and add 4
pcstor	"000" & "010000" & "0" & "00" & "00000" & "0000" & "0000" & "0000"	store the new pc into the pc

Finite State Machine Diagram

Simplified Processor Diagram

UPDATE FOR JUDE

• Docstrings added to rust assembly file
• Added memfile.dat under the assembly folder
• Updated main.sea to be that of FP4. This is a commented, complete, and functional program
• Updated the registers to be accurate to the machine
• Updated the instruction set to be accurate to the machine
• Added better FSM
• Added State Machine table
• Added Control Signals