nihargowdakm / BIST-Design Public

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Done as a part of the coursework, Design For Testing and Testability. Designed and implemented in Verilog to add Built in Self Test (BIST) capabilities to a given combinational logic. The Test Pattern Generator (TPG), Output Response Analyzer (ORA) and BIST controller were designed. A 1-bit full adder was considered as the circuit under test.

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Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
BIST_controller.v		BIST_controller.v
BIST_controller_tb.v		BIST_controller_tb.v
Bist_arch.png		Bist_arch.png
CUT.v		CUT.v
CUT_tb.v		CUT_tb.v
LFSR.v		LFSR.v
LFSR_tb.v		LFSR_tb.v
MISR.v		MISR.v
MISR_tb.v		MISR_tb.v
README.md		README.md
bist_report.pdf		bist_report.pdf