updated README to render the repo structure in a clearer way

README.md

@@ -8,15 +8,6 @@
 - parameterizable timing generator, default values correspond to VGA 640 x 480 @ 60 Hz Industry standard timing
 - image generator generates a standard test frame
 
--- RTL code in:
-- [VHDL](https://github.com/npatsiatzis/vga/tree/main/rtl/VHDL)
-- [SystemVerilog](https://github.com/npatsiatzis/vga/tree/main/rtl/SystemVerilog)
-
--- Functional verification with methodologies:
-- [cocotb](https://github.com/npatsiatzis/vga/tree/main/cocotb_sim)
-- [pyuvm](https://github.com/npatsiatzis/vga/tree/main/formal)
-- [verilator](https://github.com/npatsiatzis/vga/tree/main/verilator_sim)
-
 
 ### Repo Structure
 
@@ -31,7 +22,7 @@ This is a short tabular description of the contents of each folder in the repo.
 | [formal](https://github.com/npatsiatzis/vga/tree/main/formal) | Formal Verification using  PSL properties and [YoysHQ/sby](https://github.com/YosysHQ/oss-cad-suite-build) |
 
 
-This is <!-- the tree view of the strcture of the repo.
+This is the tree view of the strcture of the repo.
 <pre>
 <font size = "2">
 .
@@ -49,4 +40,4 @@ This is <!-- the tree view of the strcture of the repo.
 └── <font size = "4"><b><a href="https://github.com/npatsiatzis/vga/tree/main/formal">formal</a></b></font>
     ├── Makefile
     └── PSL properties file, scripts
-</pre> -->
+</pre>