Fix BaseModule call in vmm modules

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
npmitche · Oct 31, 2023 · 97ae470 · 97ae470
1 parent 9a32ef5
commit 97ae470
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Showing 9 changed files with 9 additions and 9 deletions.
diff --git a/chipsec/modules/tools/vmm/hv/hypercallfuzz.py b/chipsec/modules/tools/vmm/hv/hypercallfuzz.py
@@ -47,7 +47,7 @@
 
 class HypercallFuzz(BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x6dc9bb0, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.html')
 
     def usage(self):

diff --git a/chipsec/modules/tools/vmm/iofuzz.py b/chipsec/modules/tools/vmm/iofuzz.py
@@ -78,7 +78,7 @@
 
 class iofuzz(BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x485df2e, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.iofuzz.html')
 
     def fuzz_ports(self, iterations, write_count, random_order=False):

diff --git a/chipsec/modules/tools/vmm/msr_fuzz.py b/chipsec/modules/tools/vmm/msr_fuzz.py
@@ -79,7 +79,7 @@
 
 class msr_fuzz (BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x2e31482, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.msr_fuzz.html')
 
     def fuzz_MSRs(self, msr_addr_start, random_order=False):

diff --git a/chipsec/modules/tools/vmm/pcie_fuzz.py b/chipsec/modules/tools/vmm/pcie_fuzz.py
@@ -77,7 +77,7 @@
 
 class pcie_fuzz(BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x61c1431, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_fuzz.html')
 
     def fuzz_io_bar(self, bar, size=0x100):

diff --git a/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py b/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py
@@ -66,7 +66,7 @@
 
 class pcie_overlap_fuzz(BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x19702b2, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.html')
 
     def overlap_mmio_range(self, bus1, dev1, fun1, is64bit1, off1, bus2, dev2, fun2, is64bit2, off2, direction):

diff --git a/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py b/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py
@@ -48,7 +48,7 @@
 
 class vbox_crash_apicbase(BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x14428af, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.html')
 
     def run(self, module_argv):

diff --git a/chipsec/modules/tools/vmm/venom.py b/chipsec/modules/tools/vmm/venom.py
@@ -60,7 +60,7 @@
 
 class venom (BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x6e48a35, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.venom.html')
 
     def venom_impl(self):

diff --git a/chipsec/modules/tools/vmm/xen/hypercallfuzz.py b/chipsec/modules/tools/vmm/xen/hypercallfuzz.py
@@ -57,7 +57,7 @@
 
 class HypercallFuzz(BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x9e42fe3, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.hypercallfuzz.html')
 
     def usage(self):

diff --git a/chipsec/modules/tools/vmm/xen/xsa188.py b/chipsec/modules/tools/vmm/xen/xsa188.py
@@ -52,7 +52,7 @@
 
 class xsa188(BaseModule):
     def __init__(self):
-        BaseModule().__init__()
+        BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x13a3575, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.xsa188.html')
 
     def run(self, module_argv):