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Pull requests list

o1vm/mips: use biguint instead of Fp in witness builder
#2854 opened Nov 25, 2024 by dannywillems • Draft
implementation for add upper immediate in riscv32im
#2853 opened Nov 25, 2024 by svv232 Loading…
1
implementation for load upper immediate in riscv32im
#2852 opened Nov 25, 2024 by svv232 Loading…
1
implementation for riscv32im store word
#2851 opened Nov 25, 2024 by svv232 Loading…
1
implementation for store half instruction in riscv32im
#2850 opened Nov 25, 2024 by svv232 Loading…
1
o1vm: reorganize dependencies in alphabetical order [no-op]
#2849 opened Nov 25, 2024 by dannywillems Loading…
1
implementation for store byte instruction riscv32im
#2848 opened Nov 25, 2024 by svv232 Loading…
1
fix stype instruction parsing in riscv32im
#2847 opened Nov 25, 2024 by svv232 Loading…
1
implementation for less than immediate unsigned riscv32im
#2846 opened Nov 25, 2024 by svv232 Loading…
1
o1vm/riscv32im: test decoding remu
#2845 opened Nov 25, 2024 by dannywillems Loading…
1
implementation for set less than immediate
#2844 opened Nov 25, 2024 by svv232 Loading…
1
o1vm/riscv32im: test decoding rem
#2843 opened Nov 25, 2024 by dannywillems Loading…
1
o1vm/riscv32im: test decoding divu
#2842 opened Nov 25, 2024 by dannywillems Loading…
1
implementation for shift right arithmetic immediate for riscv32im
#2841 opened Nov 25, 2024 by svv232 Loading…
1
o1vm/riscv32im: test decoding div
#2840 opened Nov 25, 2024 by dannywillems Loading…
1
o1vm/riscv32im: test decoding mulhu
#2839 opened Nov 25, 2024 by dannywillems Loading…
1
implementation for shift right logical immediate riscv32im
#2838 opened Nov 25, 2024 by svv232 Loading…
1
o1vm/riscv32im: test decoding mulhsu
#2837 opened Nov 25, 2024 by dannywillems Loading…
1
implementation for shift left logical immediate riscv32im
#2836 opened Nov 25, 2024 by svv232 Loading…
1
o1vm/riscv32im: test decoding mulh
#2835 opened Nov 25, 2024 by dannywillems Loading…
1
o1vm/riscv32im: test decoding mul
#2834 opened Nov 25, 2024 by dannywillems Loading…
1
implementation for load half unsigned riscv32im
#2833 opened Nov 25, 2024 by svv232 Loading…
1
o1vm/riscv32im: decode M instruction type
#2832 opened Nov 25, 2024 by dannywillems Loading…
1
implementation for load byte unsigned riscv32im
#2831 opened Nov 25, 2024 by svv232 Loading…
1
o1vm/riscv32im: test decoding and
#2830 opened Nov 25, 2024 by dannywillems Loading…
1
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