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CXL detection #554
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Notes for putting CXL info in DAX and NUMA nodes: For CXL RAM: For CXL PMEM: |
By the way, if we locate CXL devices behind DAX/NUMA from them, we could use their PCI NUMA locality in case the DAX locality isn't correctly set (it's the case for CXL RAM device in Qemu+Linux 6.2 right now). |
There can be multiple entries if the region is interleaved. Might be better to merge into a single info attr? We'll see. The corresponding Linux code (CXL volatile regions) is planned for Linux 6.3. Refs open-mpi#554 Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
There can be multiple entries if the region is interleaved. Might be better to merge into a single info attr? We'll see. This uses "memregion" identifiers (regionX) to match dax devices and CXL devices. The corresponding Linux code (CXL volatile regions) is planned for Linux 6.3. Refs open-mpi#554 Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
There can be multiple entries if the region is interleaved. Might be better to merge into a single info attr? We'll see. This uses "memregion" identifiers (regionX) to match dax devices and CXL devices. The corresponding Linux code (CXL volatile regions) is planned for Linux 6.3. Refs open-mpi#554 Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
There can be multiple entries if the region is interleaved. Might be better to merge into a single info attr? We'll see. This uses "memregion" identifiers (regionX) to match dax devices and CXL devices. The corresponding Linux code (CXL volatile regions, etc) is planned for Linux 6.3. Refs open-mpi#554 Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
There can be multiple entries if the region is interleaved. Might be better to merge into a single info attr? We'll see. This uses "memregion" identifiers (regionX) to match dax devices and CXL devices. The corresponding Linux code (CXL volatile regions, etc) is planned for Linux 6.3. Refs open-mpi#554 Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
There can be multiple entries if the region is interleaved. Might be better to merge into a single info attr? We'll see. This uses "memregion" identifiers (regionX) to match dax devices and CXL devices. The corresponding Linux code (CXL volatile regions, etc) is planned for Linux 6.3. Refs #554 Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr> (cherry picked from commit aa26f29)
Starting with 2.9 (or 2.8.1) CXL memory expanders (Type 3) are detected and non-ignored (they have a dedicated PCI class 0x0502). It's not clear whether CXL Type 2 (accelerators with coherent memory) or Type 1 (devices with coherent access to host memory) will have a dedicated PCI class. If not, we'll need to dig into sysfs and/or the (non-root) PCI config space to find out whether a PCI Bridge or Device is CXL or not.
For now, they are exposed as normal PCI objects. We could switch them to CXL objects instead, either with a "CXL" subtype (for PCIDev and bridges?) and/or with a CXL upstream/downstream type (in bridges only). It's not clear whether it's useful/important or not.
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