Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Kernel fixes for openbmc #3

Merged
merged 2 commits into from
Oct 16, 2015
Merged

Kernel fixes for openbmc #3

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
5eeaca7
arm/mach-aspeed: Enable UART clock divisor
jk-ozlabs Oct 16, 2015
d819b47
arm/aspeed_defconfig: change CONFIG_USB_G_SERIAL to y
jk-ozlabs Oct 16, 2015
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion arch/arm/configs/aspeed_defconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_SERIAL=y
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_NEW_LEDS=y
Expand Down
10 changes: 10 additions & 0 deletions arch/arm/mach-aspeed/aspeed.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,8 @@ static void udbg_uart_putc(char c)

static void __init aspeed_init_early(void)
{
u32 reg;

// XXX UART stuff to fix to pinmux & co
printk("UART IO MUX...\n");
writel(0x02010023, AST_IO(AST_BASE_LPC | 0x9c));
Expand All @@ -137,6 +139,14 @@ static void __init aspeed_init_early(void)
writel(0xcb000000, AST_IO(AST_BASE_SCU | 0x80));
writel(0x00fff0c0, AST_IO(AST_BASE_SCU | 0x84));
writel(0x10CC5E80, AST_IO(AST_BASE_SCU | 0x0c));

/* We enable the UART clock divisor in the SCU's misc control
* register, as the baud rates in aspeed.dtb all assume that the
* divisor is active
*/
reg = readl(AST_IO(AST_BASE_SCU | 0x2c));
writel(reg | 0x00001000, AST_IO(AST_BASE_SCU | 0x2c));

printk("DONE, MUX=%08x %08x\n", readl(AST_IO(AST_BASE_SCU | 0x80)),
readl(AST_IO(AST_BASE_SCU | 0x84)));
printk("CLOCK_CTRL=%08x\n", readl(AST_IO(AST_BASE_SCU)));
Expand Down