sync with base: For macppc, add missing CFI for cr2, cr3, cr4

clang -S was missing a line like ".cfi_offset cr2, -16" in functions that spill cr2 (or cr3, cr4) to the stack. This was breaking a few C++ exceptions. This fix adds the missing CFI. llvm/llvm-project#83098 ok robert@ (maintainer)
openbsd · Mar 4, 2024 · 988b779 · 988b779
1 parent a8d634a
commit 988b779
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Showing 6 changed files with 45 additions and 6 deletions.
diff --git a/devel/llvm/13/Makefile b/devel/llvm/13/Makefile
@@ -2,7 +2,7 @@ LLVM_MAJOR =	13
 LLVM_VERSION =	${LLVM_MAJOR}.0.0
 LLVM_PKGSPEC =	>=13,<14
 
-REVISION-main =		25
+REVISION-main =		26
 REVISION-lldb =		5
 REVISION-python =	4
 

diff --git a/devel/llvm/13/patches/patch-llvm_lib_Target_PowerPC_PPCFrameLowering_cpp b/devel/llvm/13/patches/patch-llvm_lib_Target_PowerPC_PPCFrameLowering_cpp
@@ -11,7 +11,20 @@ Index: llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  #include "PPCSubtarget.h"
  #include "PPCTargetMachine.h"
  #include "llvm/ADT/Statistic.h"
-@@ -2696,4 +2697,8 @@ bool PPCFrameLowering::enableShrinkWrapping(const Mach
+@@ -1184,12 +1185,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
+       if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
+         continue;
+
+-      // For SVR4, don't emit a move for the CR spill slot if we haven't
+-      // spilled CRs.
+-      if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
+-          && !MustSaveCR)
+-        continue;
+-
+       // For 64-bit SVR4 when we have spilled CRs, the spill location
+       // is SP+8, not a frame-relative slot.
+       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
+@@ -2696,4 +2691,8 @@ bool PPCFrameLowering::enableShrinkWrapping(const Mach
    if (MF.getInfo<PPCFunctionInfo>()->shrinkWrapDisabled())
      return false;
    return !MF.getSubtarget<PPCSubtarget>().is32BitELFABI();

diff --git a/devel/llvm/16/Makefile b/devel/llvm/16/Makefile
@@ -2,7 +2,7 @@ LLVM_MAJOR =	16
 LLVM_VERSION =	${LLVM_MAJOR}.0.6
 LLVM_PKGSPEC =	>=16,<17
 
-REVISION-main =		23
+REVISION-main =		24
 REVISION-lldb =		3
 REVISION-python =	1
 

diff --git a/devel/llvm/16/patches/patch-llvm_lib_Target_PowerPC_PPCFrameLowering_cpp b/devel/llvm/16/patches/patch-llvm_lib_Target_PowerPC_PPCFrameLowering_cpp
@@ -9,7 +9,20 @@ Index: llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  #include "PPCSubtarget.h"
  #include "PPCTargetMachine.h"
  #include "llvm/ADT/Statistic.h"
-@@ -2711,4 +2712,8 @@ bool PPCFrameLowering::enableShrinkWrapping(const Mach
+@@ -1192,12 +1193,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
+       if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
+         continue;
+
+-      // For SVR4, don't emit a move for the CR spill slot if we haven't
+-      // spilled CRs.
+-      if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
+-          && !MustSaveCR)
+-        continue;
+-
+       // For 64-bit SVR4 when we have spilled CRs, the spill location
+       // is SP+8, not a frame-relative slot.
+       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
+@@ -2711,4 +2706,8 @@ bool PPCFrameLowering::enableShrinkWrapping(const Mach
    if (MF.getInfo<PPCFunctionInfo>()->shrinkWrapDisabled())
      return false;
    return !MF.getSubtarget<PPCSubtarget>().is32BitELFABI();

diff --git a/devel/llvm/17/Makefile b/devel/llvm/17/Makefile
@@ -2,7 +2,7 @@ LLVM_MAJOR =	17
 LLVM_VERSION =	${LLVM_MAJOR}.0.6
 LLVM_PKGSPEC =	>=17,<18
 
-REVISION-main =	4
+REVISION-main =	5
 
 SHARED_LIBS +=	LTO		0.0 \
 		Remarks		0.0 \

diff --git a/devel/llvm/17/patches/patch-llvm_lib_Target_PowerPC_PPCFrameLowering_cpp b/devel/llvm/17/patches/patch-llvm_lib_Target_PowerPC_PPCFrameLowering_cpp
@@ -9,7 +9,20 @@ Index: llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  #include "PPCSubtarget.h"
  #include "PPCTargetMachine.h"
  #include "llvm/ADT/Statistic.h"
-@@ -2739,4 +2740,8 @@ bool PPCFrameLowering::enableShrinkWrapping(const Mach
+@@ -1191,12 +1192,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &M
+       if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
+         continue;
+
+-      // For SVR4, don't emit a move for the CR spill slot if we haven't
+-      // spilled CRs.
+-      if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
+-          && !MustSaveCR)
+-        continue;
+-
+       // For 64-bit SVR4 when we have spilled CRs, the spill location
+       // is SP+8, not a frame-relative slot.
+       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
+@@ -2739,4 +2734,8 @@ bool PPCFrameLowering::enableShrinkWrapping(const Mach
    if (MF.getInfo<PPCFunctionInfo>()->shrinkWrapDisabled())
      return false;
    return !MF.getSubtarget<PPCSubtarget>().is32BitELFABI();