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fix some bad assignments and lint warning related to RVFI feature (#1947
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@yanicasa
yanicasa authored Mar 20, 2024
1 parent c76b29a commit 9ecdaa1
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Showing 2 changed files with 87 additions and 38 deletions.
121 changes: 85 additions & 36 deletions core/cva6_rvfi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -31,15 +31,8 @@ module cva6_rvfi

);

// ------------------------------------------
// CVA6 configuration
// ------------------------------------------
// Extended config
localparam bit RVF = (CVA6Cfg.IS_XLEN64 | CVA6Cfg.IS_XLEN32) & CVA6Cfg.FpuEn;
localparam bit RVD = (CVA6Cfg.IS_XLEN64 ? 1 : 0) & CVA6Cfg.FpuEn;
localparam bit FpPresent = RVF | RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8;

localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
localparam logic [CVA6Cfg.XLEN-1:0] IsaCode =
(CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
| (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
| (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
| (CVA6Cfg.XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
Expand Down Expand Up @@ -74,7 +67,7 @@ module cva6_rvfi
logic [CVA6Cfg.XLEN-1:0] rs2_forwarding;

logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] commit_instr_pc;
fu_op [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_instr_op;
fu_op [CVA6Cfg.NrCommitPorts-1:0] commit_instr_op;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd;
Expand Down Expand Up @@ -246,7 +239,7 @@ module cva6_rvfi
always_comb begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
logic exception;
exception = commit_instr_valid[i] && ex_commit_valid;
exception = commit_instr_valid[i][0] && ex_commit_valid;
rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit_valid) ||
(exception && (ex_commit_cause == riscv::ENV_CALL_MMODE ||
ex_commit_cause == riscv::ENV_CALL_SMODE ||
Expand All @@ -260,7 +253,7 @@ module cva6_rvfi
rvfi_instr_o[i].rs1_addr = commit_instr_rs1[i][4:0];
rvfi_instr_o[i].rs2_addr = commit_instr_rs2[i][4:0];
rvfi_instr_o[i].rd_addr = commit_instr_rd[i][4:0];
rvfi_instr_o[i].rd_wdata = (FpPresent && is_rd_fpr(commit_instr_op[i])) ?
rvfi_instr_o[i].rd_wdata = (CVA6Cfg.FpPresent && is_rd_fpr(commit_instr_op[i])) ?
commit_instr_result[i] : wdata[i];
rvfi_instr_o[i].pc_rdata = commit_instr_pc[i];
rvfi_instr_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr;
Expand All @@ -284,27 +277,47 @@ module cva6_rvfi
always_comb begin

rvfi_csr_o.fflags = CVA6Cfg.FpPresent ?
'{rdata: {'0, csr.fcsr_q.fflags}, wdata: {'0, csr.fcsr_q.fflags}, rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 5{1'b0}}, csr.fcsr_q.fflags},
wdata: {{CVA6Cfg.XLEN - 5{1'b0}}, csr.fcsr_q.fflags},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.frm = CVA6Cfg.FpPresent ?
'{rdata: {'0, csr.fcsr_q.frm}, wdata: {'0, csr.fcsr_q.frm}, rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 3{1'b0}}, csr.fcsr_q.frm},
wdata: {{CVA6Cfg.XLEN - 3{1'b0}}, csr.fcsr_q.frm},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.fcsr = CVA6Cfg.FpPresent ?
'{
rdata: {'0, csr.fcsr_q.frm, csr.fcsr_q.fflags},
wdata: {'0, csr.fcsr_q.frm, csr.fcsr_q.fflags},
rdata: {{CVA6Cfg.XLEN - 8{1'b0}}, csr.fcsr_q.frm, csr.fcsr_q.fflags},
wdata: {{CVA6Cfg.XLEN - 8{1'b0}}, csr.fcsr_q.frm, csr.fcsr_q.fflags},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.ftran = CVA6Cfg.FpPresent ?
'{rdata: {'0, csr.fcsr_q.fprec}, wdata: {'0, csr.fcsr_q.fprec}, rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 7{1'b0}}, csr.fcsr_q.fprec},
wdata: {{CVA6Cfg.XLEN - 7{1'b0}}, csr.fcsr_q.fprec},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.dcsr = CVA6Cfg.DebugEn ?
'{rdata: {'0, csr.dcsr_q}, wdata: {'0, csr.dcsr_q}, rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.dcsr_q},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.dcsr_q},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.dpc = CVA6Cfg.DebugEn ?
'{rdata: {csr.dpc_q}, wdata: csr.dpc_q, rmask: '1, wmask: '1}
'{rdata: csr.dpc_q, wdata: csr.dpc_q, rmask: '1, wmask: '1}
: '0;
rvfi_csr_o.dscratch0 = CVA6Cfg.DebugEn ?
'{rdata: csr.dscratch0_q, wdata: csr.dscratch0_q, rmask: '1, wmask: '1}
Expand Down Expand Up @@ -377,25 +390,31 @@ module cva6_rvfi
rvfi_csr_o.mtval = '{rdata: csr.mtval_q, wdata: csr.mtval_q, rmask: '1, wmask: '1};
rvfi_csr_o.mip = '{rdata: csr.mip_q, wdata: csr.mip_q, rmask: '1, wmask: '1};
rvfi_csr_o.menvcfg = '{
rdata: {'0, csr.fiom_q},
wdata: {'0, csr.fiom_q},
rdata: {{CVA6Cfg.XLEN - 1{1'b0}}, csr.fiom_q},
wdata: {{CVA6Cfg.XLEN - 1{1'b0}}, csr.fiom_q},
rmask: '1,
wmask: '1
};
rvfi_csr_o.menvcfgh = CVA6Cfg.XLEN == 32 ?
'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
: '0;
rvfi_csr_o.mvendorid = '{
rdata: OPENHWGROUP_MVENDORID,
wdata: OPENHWGROUP_MVENDORID,
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID},
rmask: '1,
wmask: '1
};
rvfi_csr_o.marchid = '{rdata: ARIANE_MARCHID, wdata: ARIANE_MARCHID, rmask: '1, wmask: '1};
rvfi_csr_o.marchid = '{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID},
rmask: '1,
wmask: '1
};

rvfi_csr_o.mhartid = '{rdata: hart_id_i, wdata: hart_id_i, rmask: '1, wmask: '1};
rvfi_csr_o.mcountinhibit = '{
rdata: {'0, csr.mcountinhibit_q},
wdata: {'0, csr.mcountinhibit_q},
rdata: {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, csr.mcountinhibit_q},
wdata: {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, csr.mcountinhibit_q},
rmask: '1,
wmask: '1
};
Expand All @@ -406,7 +425,12 @@ module cva6_rvfi
wmask: '1
};
rvfi_csr_o.mcycleh = CVA6Cfg.XLEN == 32 ?
'{rdata: csr.cycle_q[63:32], wdata: csr.cycle_q[63:32], rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.minstret = '{
rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
Expand All @@ -415,7 +439,12 @@ module cva6_rvfi
wmask: '1
};
rvfi_csr_o.minstreth = CVA6Cfg.XLEN == 32 ?
'{rdata: csr.instret_q[63:32], wdata: csr.instret_q[63:32], rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.cycle = '{
rdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
Expand All @@ -424,7 +453,12 @@ module cva6_rvfi
wmask: '1
};
rvfi_csr_o.cycleh = CVA6Cfg.XLEN == 32 ?
'{rdata: csr.cycle_q[63:32], wdata: csr.cycle_q[63:32], rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.instret = '{
rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
Expand All @@ -433,7 +467,12 @@ module cva6_rvfi
wmask: '1
};
rvfi_csr_o.instreth = CVA6Cfg.XLEN == 32 ?
'{rdata: csr.instret_q[63:32], wdata: csr.instret_q[63:32], rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.dcache = '{rdata: csr.dcache_q, wdata: csr.dcache_q, rmask: '1, wmask: '1};
rvfi_csr_o.icache = '{rdata: csr.icache_q, wdata: csr.icache_q, rmask: '1, wmask: '1};
Expand All @@ -447,7 +486,12 @@ module cva6_rvfi
wmask: '1
};
rvfi_csr_o.pmpcfg1 = CVA6Cfg.XLEN == 32 ?
'{rdata: csr.pmpcfg_q[7:4], wdata: csr.pmpcfg_q[7:4], rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[7:4]},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[7:4]},
rmask: '1,
wmask: '1
}
: '0;
rvfi_csr_o.pmpcfg2 = '{
rdata: csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8],
Expand All @@ -456,17 +500,22 @@ module cva6_rvfi
wmask: '1
};
rvfi_csr_o.pmpcfg3 = CVA6Cfg.XLEN == 32 ?
'{rdata: csr.pmpcfg_q[15:12], wdata: csr.pmpcfg_q[15:12], rmask: '1, wmask: '1}
'{
rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[15:12]},
wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[15:12]},
rmask: '1,
wmask: '1
}
: '0;

for (int i = 0; i < 16; i++) begin
rvfi_csr_o.pmpaddr[i] = '{
rdata:
csr.pmpcfg_q[i].addr_mode[1]
== 1'b1 ?
{'0, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
: {
'0
{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
,
csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
,
Expand All @@ -475,9 +524,9 @@ module cva6_rvfi
wdata:
csr.pmpcfg_q[i].addr_mode[1]
== 1'b1 ?
{'0, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
: {
'0
{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
,
csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
,
Expand Down
4 changes: 2 additions & 2 deletions core/include/rvfi_types.svh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -106,12 +106,12 @@
logic [Cfg.XLEN-1:0] rs1_forwarding; \
logic [Cfg.XLEN-1:0] rs2_forwarding; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_pc; \
ariane_pkg::fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.TRANS_ID_BITS-1:0] commit_instr_op; \
ariane_pkg::fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr_op; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs1; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs2; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rd; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.XLEN-1:0] commit_instr_result; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_valid; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr_valid; \
logic [Cfg.XLEN-1:0] ex_commit_cause; \
logic ex_commit_valid; \
riscv::priv_lvl_t priv_lvl; \
Expand Down

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