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    18 repositories

    • wr-cores

      Public
      VHDL
      •0•0•0•0•Updated Dec 23, 2024Dec 23, 2024

    • general-cores

      Public
      VHDL
      •0•0•0•1•Updated Dec 6, 2024Dec 6, 2024

    • pyftdi

      Public
      FTDI device driver written in pure Python
      Python
      •
      Other
      •216•0•0•0•Updated Nov 20, 2024Nov 20, 2024

    • openFPGALoader

      Public
      Universal utility for programming FPGA
      C++
      •
      Apache License 2.0
      •272•0•0•0•Updated Nov 7, 2024Nov 7, 2024

    • edalize-plugins

      Public
      Python
      •0•0•0•0•Updated Oct 11, 2024Oct 11, 2024

    • cheby

      Public
      Cloned from https://gitlab.cern.ch/be-cem-edl/common/cheby
      VHDL
      •
      GNU General Public License v3.0
      •0•0•0•0•Updated Sep 27, 2024Sep 27, 2024

    • etherbone-core

      Public
      C
      •0•0•0•0•Updated Sep 23, 2024Sep 23, 2024

    • renode

      Public
      Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
      RobotFramework
      •
      Other
      •301•0•0•0•Updated Sep 18, 2024Sep 18, 2024

    • renode-infrastructure

      Public
      C#
      •133•0•0•0•Updated Sep 18, 2024Sep 18, 2024

    • fusesoc

      Public
      Package manager and build abstraction tool for FPGA/ASIC development
      Python
      •
      BSD 2-Clause "Simplified" License
      •254•0•0•0•Updated Sep 6, 2024Sep 6, 2024

    • renode-dpi-examples

      Public
      CMake
      •
      Apache License 2.0
      •2•0•0•0•Updated Jul 4, 2024Jul 4, 2024

    • edalize

      Public
      An abstraction library for interfacing EDA tools
      Python
      •
      BSD 2-Clause "Simplified" License
      •194•0•0•0•Updated Jun 24, 2024Jun 24, 2024

    • peakrdl-sv

      Public
      A SystemRDL exporter for SystemVerilog
      Python
      •
      MIT License
      •1•1•0•0•Updated Jun 21, 2024Jun 21, 2024

    • pyrenode3

      Public
      Python
      •
      Apache License 2.0
      •6•0•0•0•Updated Jun 15, 2024Jun 15, 2024

    • cute-a7-wrf

      Public
      cute a7 example design
      VHDL
      •3•0•0•0•Updated Apr 16, 2024Apr 16, 2024

    • urv-core

      Public
      The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs
      C
      •0•0•0•0•Updated Feb 5, 2024Feb 5, 2024

    • PeakRDL

      Public
      Control and status register code generator toolchain
      Python
      •
      GNU General Public License v3.0
      •25•0•0•0•Updated Nov 8, 2023Nov 8, 2023

    • rtd-tutorial-template

      Public template
      Template for the Read the Docs tutorial
      Python
      •1.5k•0•0•0•Updated Oct 2, 2023Oct 2, 2023