ECE 5745 Complex Digital ASIC Design

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17 repositories

ece5745-tapeout
Public
Verilog
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Apache License 2.0
•0•3•0•0•Updated Jul 25, 2023Jul 25, 2023
project-group99
Public
Aidan Mcnay
Python
•0•1•0•0•Updated Jul 23, 2023Jul 23, 2023
example-custom-test-harness
Public
Verilog
•0•0•0•0•Updated May 10, 2023May 10, 2023
example-import-port-array
Public
An example about how to import a Verilog module with an array of ports
Python
•0•0•0•0•Updated Apr 30, 2023Apr 30, 2023
example-gate-level-design
Public
Verilog
•0•0•0•0•Updated Apr 28, 2023Apr 28, 2023
ece5745-S05-srams
Public
Section 05: SRAM Generators
Verilog
•0•1•0•0•Updated Mar 3, 2023Mar 3, 2023
ece5745-S01-front-end
Public
Section 01: ASIC Flow Front-End
Verilog
•3•2•0•0•Updated Mar 3, 2023Mar 3, 2023
ece5745-S02-back-end
Public
Section 02: ASIC Flow Back-End
Verilog
•1•0•0•0•Updated Mar 3, 2023Mar 3, 2023
example-method-ifcs
Public
Example of using method-based interfaces in Verilog with Python wrappers
Verilog
•0•1•0•0•Updated Feb 17, 2023Feb 17, 2023
ece5745-tut4-asic-tools
Public
ECE 5745 Tutorial 4: Synopsys/Cadence ASIC Tools
Verilog
•1•0•0•0•Updated Feb 4, 2023Feb 4, 2023
example-bluespec
Public
Bluespec Example
Bluespec
•0•0•0•0•Updated Feb 3, 2023Feb 3, 2023
ece5745-tut10-spice
Public
ECE 5745 Tutorial 10: SPICE Simulation
SourcePawn
•0•2•0•0•Updated Mar 23, 2022Mar 23, 2022
ece5745-tut8-sram
Public
ECE 5745 Tutorial 8: SRAM Generators
Verilog
•2•13•0•0•Updated Mar 5, 2022Mar 5, 2022
ece5745-tut6-asic-flow
Public
ECE 5745 Tutorial 6: Automated ASIC Flow
Verilog
•4•7•0•0•Updated Feb 4, 2022Feb 4, 2022
ece5745-tut2-git
Public
ECE 5745 Tutorial 2: Git Distributed Version Control System
9•0•0•2•Updated Jan 31, 2022Jan 31, 2022
ece5745-tut3-pymtl
Public
ECE 5745 Tutorial 3: PyMTL3 Hardware Modeling Framework
Python
•33•1•0•0•Updated Jun 4, 2021Jun 4, 2021
example-src-sink-testing
Public
Example of PyMTL3 source/sink testing
Verilog
•0•0•0•0•Updated May 7, 2020May 7, 2020