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    216 repositories

    • IHP-Open-PDK

      Public
      130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      HTML
      •
      Apache License 2.0
      •65•0•1•0•Updated Nov 28, 2024Nov 28, 2024

    • EF_PSRAM_CTRL_V2

      Public
      Verilog
      •
      Apache License 2.0
      •0•1•3•0•Updated Nov 27, 2024Nov 27, 2024

    • ipm

      Public
      Open-source IPs Package Manager (IPM)
      Python
      •
      Apache License 2.0
      •2•14•5•2•Updated Nov 27, 2024Nov 27, 2024

    • sky130_ef_ip__adc3v_12bit

      Public
      12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.
      Verilog
      •
      Apache License 2.0
      •2•0•0•0•Updated Nov 27, 2024Nov 27, 2024

    • sky130_ef_ip__ccomp3v

      Public
      Continuous analog comparator, 1mV resolution
      Tcl
      •
      Apache License 2.0
      •2•0•0•0•Updated Nov 27, 2024Nov 27, 2024

    • sky130_ef_ip__cdac3v_12bit

      Public
      12-bit capacitive DAC
      Tcl
      •2•0•0•0•Updated Nov 27, 2024Nov 27, 2024

    • sky130_ef_ip__analog_switches

      Public
      Set of analog switch circuits for general-purpose use
      Shell
      •
      Apache License 2.0
      •2•0•0•0•Updated Nov 27, 2024Nov 27, 2024

    • sky130_ef_ip__samplehold

      Public
      Analog 3.3V sample and hold circuit, with buffered output
      Tcl
      •
      Apache License 2.0
      •2•0•0•0•Updated Nov 27, 2024Nov 27, 2024

    • sky130_ef_ip__template

      Public template
      A template repository for analog designs to ensure consistency and interoperability between IP blocks.
      Apache License 2.0
      •0•0•0•0•Updated Nov 27, 2024Nov 27, 2024

    • skywater-pdk-libs-sky130_fd_pr

      Public
      Python
      •
      Apache License 2.0
      •24•5•7•0•Updated Nov 27, 2024Nov 27, 2024

    • tt-fpga-hdl-demo

      Public template
      Python
      •
      Apache License 2.0
      •5•1•0•0•Updated Nov 27, 2024Nov 27, 2024

    • chipcraft---mest-course

      Public
      TL-Verilog
      •
      Creative Commons Zero v1.0 Universal
      •7•29•0•0•Updated Nov 26, 2024Nov 26, 2024

    • cace-action

      Public
      GitHub composite action for CACE
      Apache License 2.0
      •0•0•0•0•Updated Nov 26, 2024Nov 26, 2024

    • sky130_ef_ip__opamp

      Public
      Instrumentation amplifier (analog IP example)
      Verilog
      •
      Apache License 2.0
      •4•0•0•0•Updated Nov 26, 2024Nov 26, 2024

    • caravel_mgmt_soc_litex

      Public
      https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
      Verilog
      •
      Apache License 2.0
      •15•26•25•14•Updated Nov 26, 2024Nov 26, 2024

    • openlane-metrics

      Public
      Repository to store metric results for OpenLane 2.0.0+
      0•0•0•0•Updated Nov 25, 2024Nov 25, 2024

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      flowasicedaverilogvlsipnrsiliconlvsflowssta
      Python
      •
      Apache License 2.0
      •38•217•67•14•Updated Nov 25, 2024Nov 25, 2024

    • sky130_pa_ip__instramp

      Public
      Instrumentation amplifier in sky130 by Phil Allen
      Tcl
      •
      Apache License 2.0
      •2•2•0•0•Updated Nov 24, 2024Nov 24, 2024

    • EF_SRAM_4096x8

      Public
      0•0•0•0•Updated Nov 22, 2024Nov 22, 2024

    • sky130_sw_ip__por

      Public
      Chipalooza challenge - bandgap-referenced Power-on-Reset (PoR)
      Shell
      •
      Apache License 2.0
      •2•1•0•1•Updated Nov 21, 2024Nov 21, 2024

    • sky130_icrg_ip__ulpcomp

      Public
      Participating IP: ULP Comparator. Designed as part of Efabless latest Caravel design.
      Tcl
      •
      Apache License 2.0
      •3•2•0•0•Updated Nov 21, 2024Nov 21, 2024

    • sky130_ak_ip__comparator

      Public
      Comparator in sky130 by Andrew Kang (Chipalooza challenge 2024)
      Shell
      •2•0•0•0•Updated Nov 21, 2024Nov 21, 2024

    • sky130_iic_ip__audiodac_v1

      Public
      Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
      Verilog
      •
      Apache License 2.0
      •5•1•0•1•Updated Nov 20, 2024Nov 20, 2024

    • openlane2-step-unit-tests

      Public
      Step-specific Unit Tests for OpenLane 2.0.0+
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Nov 19, 2024Nov 19, 2024

    • sky130_td_ip__opamp_hp

      Public
      High-gain operational amplifier for SKY130 CMOS process by Thomas Dexter (Chipalooza challenge 2024)
      Shell
      •
      Apache License 2.0
      •2•1•0•0•Updated Nov 16, 2024Nov 16, 2024

    • cace

      Public
      Circuit Automatic Characterization Engine
      Python
      •
      Apache License 2.0
      •6•45•23•2•Updated Nov 15, 2024Nov 15, 2024

    • sky130_be_ip__lsxo

      Public
      Low-speed crystal oscillator IP for the SKY130 PDK by Brady Etz (Chipalooza challenge 2024)
      PLSQL
      •
      Apache License 2.0
      •1•0•0•0•Updated Nov 14, 2024Nov 14, 2024

    • sky130_ajc_ip__brownout

      Public
      Brown-out detector for SKY130 by Robin Tsang (Chipalooza challenge 2024)
      Verilog
      •
      Apache License 2.0
      •2•0•0•0•Updated Nov 14, 2024Nov 14, 2024

    • caravel_board

      Public
      C
      •41•31•28•3•Updated Nov 14, 2024Nov 14, 2024

    • sky130_ef_ip__power_on_reset

      Public
      Power-on-reset subsystem comprising a voltage reference, LDO, and POR.
      Tcl
      •
      Apache License 2.0
      •1•1•1•0•Updated Nov 13, 2024Nov 13, 2024