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    297 repositories

    • picobello

      Public
      whatever it means
      SystemVerilog
      •
      Other
      •0•3•0•1•Updated Feb 6, 2025Feb 6, 2025

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •10•22•0•0•Updated Feb 6, 2025Feb 6, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •52•220•8•17•Updated Feb 6, 2025Feb 6, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •18•89•1•2•Updated Feb 6, 2025Feb 6, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •719•17•0•5•Updated Feb 6, 2025Feb 6, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •58•62•16•7•Updated Feb 6, 2025Feb 6, 2025

    • dumpling

      Public
      An ATE Pattern Generator for PULP chips and JTAG Taps in general
      Python
      •
      Apache License 2.0
      •2•7•0•2•Updated Feb 5, 2025Feb 5, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •6•48•0•1•Updated Feb 4, 2025Feb 4, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •13•41•1•3•Updated Feb 4, 2025Feb 4, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•116•7•5•Updated Feb 4, 2025Feb 4, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •22•69•4•5•Updated Feb 4, 2025Feb 4, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •152•567•31•9•Updated Feb 4, 2025Feb 4, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •15•5•0•6•Updated Feb 3, 2025Feb 3, 2025

    • chimera

      Public
      Python
      •
      Other
      •2•14•9•1•Updated Feb 3, 2025Feb 3, 2025

    • safety_island

      Public
      A reliable, real-time subsystem for the Carfield SoC
      C
      •
      Other
      •4•13•1•5•Updated Feb 3, 2025Feb 3, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •3•10•1•5•Updated Feb 3, 2025Feb 3, 2025

    • hero-tools

      Public
      This repository includes a set of software tools enabling heterogeneous OpenMP programming on heterogeneous platforms released by the PULP Project.
      C
      •
      Apache License 2.0
      •0•1•0•0•Updated Feb 3, 2025Feb 3, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •11•23•6•3•Updated Feb 3, 2025Feb 3, 2025

    • llvm-project

      Public
      13k•7•7•1•Updated Feb 3, 2025Feb 3, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •35•40•7•4•Updated Feb 3, 2025Feb 3, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •27•160•12•4•Updated Feb 3, 2025Feb 3, 2025

    • regression_tests

      Public
      C
      •17•7•3•1•Updated Feb 3, 2025Feb 3, 2025

    • pulpissimo

      Public
      This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      •
      Other
      •170•399•125•4•Updated Feb 1, 2025Feb 1, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •274•1.2k•44•10•Updated Jan 31, 2025Jan 31, 2025

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •41•280•26•4•Updated Jan 31, 2025Jan 31, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •68•1•0•2•Updated Jan 30, 2025Jan 30, 2025

    • gpio

      Public
      Parametric GPIO Peripheral
      SystemVerilog
      •
      Other
      •5•10•0•2•Updated Jan 30, 2025Jan 30, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •47•281•3•4•Updated Jan 30, 2025Jan 30, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •135•394•65•8•Updated Jan 29, 2025Jan 29, 2025

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •15•81•17•5•Updated Jan 29, 2025Jan 29, 2025