Restore the Netlist flow

[alaindargelas]

Restore the Netlist compilation flow.
The new Netlist compilation flow looks like the following in a raptor.tcl project:

# Gate level netlist input example

# Specifc project type "gate-level"
create_design AES_DECRYPT_GATE -type gate-level

target_device 1VG28

# Specific command to load a netlist file
read_netlist aes_decrypt.v

add_constraint_file aes_decrypt_gate.sdc

# Analyze the Verilog netlist (Hierarchy)
analyze 

# MUST: Synthesis only converts Verilog to Eblif for VPR (No optimization)
synthesize

packing
place
route
sta
power
bitstream

[codecov]

Codecov Report

Attention: Patch coverage is 0% with 10 lines in your changes are missing coverage. Please review.

Project coverage is 14.03%. Comparing base (ed2bf6a) to head (1ad8e18).

❗ Current head 1ad8e18 differs from pull request most recent head d4254ee. Consider uploading reports for the commit d4254ee to get more accurate results

Files	Patch %	Lines
src/Compiler/CompilerOpenFPGA.cpp	0.00%	7 Missing ⚠️
src/Compiler/Compiler.cpp	0.00%	3 Missing ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #1480      +/-   ##
==========================================
- Coverage   14.03%   14.03%   -0.01%     
==========================================
  Files         282      282              
  Lines       32009    32011       +2     
  Branches    18353    18354       +1     
==========================================
  Hits         4492     4492              
- Misses      26514    26516       +2     
  Partials     1003     1003              

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