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Test release dev #2
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Commits on Jul 16, 2024
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Fix typo in serial protocol docs
Fixes misspelling of `triggered` in serial protocol docs. Signed-off-by: hasheddan <georgedanielmangum@gmail.com>
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Support more recent reedsolo packages
- https://github.com/tomerfiliba-org/reedsolomon/releases/tag/v1.6.1 - this seems to be related to licenses only. - https://github.com/tomerfiliba-org/reedsolomon/releases/tag/v1.7.0 - this is related to installation. Closes espressif#872
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espefuse: Prevent burning XTS_AES and ECDSA keys into BLOCK9 (BLOCK_K…
…EY5) eFuse module has a hardware bug. It is related to ESP32-C3, C6, S3, H2 chips: - BLOCK9 (BLOCK_KEY5) can not be used by XTS_AES keys. For H2 chips, the BLOCK9 (BLOCK_KEY5) can not be used by ECDSA keys. S2 does not have such a hardware bug.
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image_info: Display disabled WP pin as disabled
The image formats know about the special value 0xee used to disable WP. Display this with image_info. E.g.: ESP32-C3 extended image header ============================== WP pin: 0xee (disabled)
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image_info: Print chip ID's name if known
Example: Flash pins drive settings: clk_drv: 0x0, q_drv: 0x0, d_drv: 0x0, cs0_drv: 0x0, hd_drv: 0x0, wp_drv: 0x0 Chip ID: 5 (ESP32-C3) Minimal chip revision: v0.0, (legacy min_rev = 0) Maximal chip revision: v655.35 An unknown ID will be printed as: Chip ID: 42 (Unknown ID)
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espefuse: Explicit setting of efuse time settings
EFUSE_PWR_ON_NUM in C3 has default value = 0x2880, now = 0x3000
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espefuse: Adds yaml efuse description files for all chip
- esptool: Updates eFuses wafer major&minor versions - esptool(esp32c6): Adds package versions - espefuse(esp32c6): Replace PKG_VERSION BLK_VERSION_MINOR BLK_VERSION_MAJOR - espefuse(esp32c6): Adds adc calib efuses - espefuse: Adds yaml files for Build with PyInstaller
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bugfix(usb_jtag_serial): Autofeed super watchdog (SWD) to avoid reset…
…s during flashing
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bugfix(espsecure): Print a clear error message if incompatible OpenSS…
…L backend is used Closes espressif#878
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esptool & espefuse: Fix byte order in MAC (for C6 and H2)
MAC: 60:55:f9:ff:fe:f7:2c:a2 (EUI64, used for IEEE802154) BASE MAC: 60:55:f9:f7:2c:a2 (used for BT) MAC_EXT: ff:fe
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feat(espsecure): Allow prompting for HSM PIN in read_hsm_config
If hsm_config does not contain "credentials" the user will be prompted for the HSM PIN. This avoids the need to have HSM PINs typed in config files which is not a good security practice. ADJUNCT: Updated documentation to reflect new usage Closes espressif#900
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fix(autodetection): Remove the ESP32-S2 ROM class from get_security_i…
…nfo autodetection
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feat(esp32-s3): Support >16MB quad flash chips
Adds support for the W25Q256 and GD25Q256 flash chips. Closes espressif#883
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feat(loader): Added hints for some serial port issues when rising por…
…t error Closes espressif/esp-idf#12366
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docs(troubleshooting): Explain issues when flashing with USB-Serial/J…
…TAG or USB-OTG Closes espressif#924
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feat(elf2image): add ram-only-header argument
The ram-only-header configuration makes only the RAM segments visible to the ROM bootloader placing them at the beginning of the file and altering the segment count from the image header with the quantity of these segments, and also writing only their checksum. This segment placement also may not result as optimal as the standard way regarding the padding gap use among the flash segments that could result in a less fragmented binary. The image built must then handle the basic hardware initialization and the flash mapping for code execution after ROM bootloader boot it. Signed-off-by: Marek Matej <marek.matej@espressif.com> Signed-off-by: Almir Okato <almir.okato@espressif.com>
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feat(xip_psram): support xip psram feature on esp32p4
Expanded IROM / DROM range to include psram space as well
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fix(load_ram): check for overlaps in bss section
Newer toolchains now store jump table in the data section which results in .bss section to be used more as well. This change should ensure that we avoid overwriting the bss section of the flasher stub when writing to RAM.
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fix(esptool): Rephrase the --ram-only-header command message
Signed-off-by: Marek Matej <marek.matej@espressif.com>
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fix(esptool): Remove the shebang from uf2_writer.py
This is not a script, so there' no need for it.
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feat(esp32c5): add target esp32c5 beta3
ROM version: 20230803
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fix(esptool): Proper alignment for SoCs with offset load
Update the --ram-only-header segments handling for the ESP32 and ESP32-S2 SoC. Signed-off-by: Marek Matej <marek.matej@espressif.com>
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fix: Index image segments from 0 instead of 1
idf.py (for example in idf.py monitor command) numbers the segments starting from 0, but current esptool.py image_view numbers them starting from 1. This MR unifies the behaviors between idf.py and esptool.py image_view --version 2 (which will be the default version of image_view in new v 5.0).
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ci(pyinstaller): Limit version to v5.3.12
PyInstaller >=6.0 seems to cause significantly more false positives from antivirus programs Closes espressif#944
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feat(espefuse): Allow the espefuse.py to work when coding scheme == 3
Signed-off-by: Francisco Blas (klondike) Izquierdo Riera <klondike@klondike.es> Closes espressif#950
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feat: Added warning when secure boot enabled
Warning message that the flash settings parameters won't be changed because of enabled secure boot
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ci(esp32c5): add host test for esp32c5
Skipped some eFuse tests because eFuse of c5 has not been supported yet
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ci: Remove the deploy_docs_production job from the scheduled pipeline
Fixes the "'deploy_docs_production' job needs 'build_docs' job, but 'build_docs' is not in any previous stage" issue.
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docs(flashing): Fixed a typo in /docs/en/esptool/flashing-firmware.rst
Updated the text in this file to fix a typo which was decives, that is now devices.
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fix: sort segments if ram_only_header is used
There are a few scenarios that segment sorting is required. This is (as for now) a zephyr-case scenario only, where flash section can be created during in-between ram linking. Without segment sorting, flash segments will overlap and ELF won't be created. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
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fix: ram_only_header: pad flash segment to next boundary
When flash segment does not fit minimum alignment requirement, pad it to next alignment boundary so that the flash placement fits properly. Otherwise ELF won't be created due to wrong alignment. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
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fix(elf2image): add ELF flags to merge condition
Improve the condition upon the segments being merged in the elf2image command. Covering the cases when comparing adjacent segment addresses and types is not enough. Signed-off-by: Marek Matej <marek.matej@espressif.com>
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fix: Do not append SHA256 when
--ram-only-header
When called with `--ram-only-header`, the ROM segments are hidden. In this case, the end of the first two visible segments (in RAM) is not the end of the image and is not suitable for appending the SHA256 digest.
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feat(espefuse): Adds efuse dump formats: separated(default) and unite…
…d(new) Added features: - read cmds can be run after burn cmds - the dump cmd can be used to create a united efuse file in --virt mode - the dump cmd can be used a few times without changing original data - updated the doc
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change(port_detection): Filter out BT and WLAN debug serial ports on …
…MacOS Related to espressif/esp-idf#14058
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ci(pre-commit): Update version of commit-linter
Update of conventional-commi-linter because of not working with Python version 3.12. UnicodeEncodeError: 'charmap' codec can't encode character '\u274c' in position 2: character maps to <undefined>
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feat(esp32c5): Add USB-serial/JTAG stub support
- Enables USB-serial/JTAG stub - Enables USE_MAX_CPU_FREQ
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Commits on Jul 18, 2024
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