Ioapic #1
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Ioapic #1
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| void ioapic_int_mask(int irq); | ||
| void ioapic_int_unmask(int irq); | ||
| // void ioapic_int_mask(int irq); | ||
| // void ioapic_int_unmask(int irq); |
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We should remove this. And make the functions in ioapic.c "static inline".
| @@ -163,6 +163,7 @@ kmain(struct multiboot *mboot, u32_t mboot_magic, u32_t esp) | |||
| kern_boot_comp(INIT_CORE); | |||
| lapic_init(); | |||
| hpet_init(); | |||
| chal_irq_enable(HW_SERIAL, 0); | |||
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This should really be a function in serial.c. Like "serial_late_init()" or "serial_irq_init()" something like that.
| * So we will configure the logical id of cores with id larger than 7 | ||
| * to 0 which means we should find out a way(x2APIC) to fix this when we | ||
| * have more than 8 cores in ioapic. | ||
| */ |
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See if you can create a ISSUE on mainline.
|
Thanks, I'll pull this. Just got a couple of minor comments, you can fix them when you get to it, no rush! I'm so happy the original IOAPIC logic didn't have bugs!! :) |
phanikishoreg
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May 13, 2018
Implement read only filesystem and tar parsing
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Summary of this Pull Request (PR)
Since xAPIC only support 8 bits logical destination bitmap, we will configure the the logical lapic ID of each cores to it's cpuid when cpuid is smaller then 8, to 0 when cpuid is larger or equal to 8.
a core will be added to an irq's bitmap when we try to enable the irq on that core. and we will remove the core from an irq's bitmap when we try to disable the irq on that core. The irq will be masked if we remove all cores from its bitmap. IMPORTANT: the chal_irq_XXX is not thread-safe which means we should not try to disable or enable the same irq on different core concurrently.
change hw_asnd_caps to 2d array.
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@phanikishoreg
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