[CoreIR] Make coreir an optional dependency (#1312)

* Remove setup.py dependency

* Remove register dependency

* Update compile.py

* Update util.py

* Update test_csr.py

* Update test_define.py

* Add ignore collect hook

* WIP Update tests

* Update tests

* Fix collection issue

* WIP update tests

* Fix rebase artifact

* Revert test changes

* Just remove imports for now

* update bind tests

* Fix circt version

* Fix version numbers

* Add optional dependency test

* update golds

* Remove version comment

* Skip coreir in tests

* Fix skip syntax

* Update bind unit test

* Update compile guard tests

* Skip more tests

* Update workflow

* Update more tests

* Update tests

* Fix test spec

* Update comments

* Update fault logic

* Remove skip logic

* Remove skip

* Add bind test

* Update line numbers

* Remove deprecated test

* Remove deploy change

.github/workflows/linux-test.yml

@@ -33,12 +33,18 @@ jobs:
         python -m pip install py
         # END: Temp fix
         python -m pip install .
-        python -m pip install flake8 pytest pytest-cov pytest-pycodestyle fault>=3.1.1
+        python -m pip install flake8 pytest pytest-cov pytest-pycodestyle
         python -m pip install importlib-resources
-        python -m pip install kratos  # test optional dependency
 
-    - name: Test with pytest
+    - name: Test without optional dependencies
       run: |
+        # Quick check to make sure mlir works without coreir installed
+        py.test tests/test_backend/test_mlir
+
+    - name: Test with optional dependencies
+      run: |
+        python -m pip install kratos coreir fault
+        # Measure full coverage here with optional dependencies
         py.test --cov magma -v --cov-report term-missing tests
         pycodestyle magma/
 

magma/compile.py

@@ -2,7 +2,6 @@
 from pathlib import PurePath
 
 from magma.backend import verilog, blif, firrtl, dot
-from magma.backend.coreir.coreir_compiler import CoreIRCompiler
 from magma.backend.mlir.mlir_compiler import MlirCompiler
 from magma.bind import bind_generators
 from magma.compile_exception import MagmaCompileException
@@ -20,6 +19,12 @@
 __all__ = ["compile"]
 
 
+def _make_coreir_compiler(main, basename, opts):
+    # Delayed import for optional dependency.
+    from magma.backend.coreir.coreir_compiler import CoreIRCompiler
+    return CoreIRCompiler(main, basename, opts)
+
+
 def _make_compiler(output, main, basename, opts):
     if output == "verilog":
         return verilog.VerilogCompiler(main, basename)
@@ -30,10 +35,10 @@ def _make_compiler(output, main, basename, opts):
     if output == "dot":
         return dot.DotCompiler(main, basename)
     if output == "coreir":
-        return CoreIRCompiler(main, basename, opts)
+        return _make_coreir_compiler(main, basename, opts)
     if output == "coreir-verilog":
         opts["output_verilog"] = True
-        return CoreIRCompiler(main, basename, opts)
+        return _make_coreir_compiler(main, basename, opts)
     if output == "mlir":
         return MlirCompiler(main, basename, opts)
     if output == "mlir-verilog":

magma/primitives/register.py

@@ -1,6 +1,5 @@
 from typing import Union
 
-import coreir
 import hwtypes as ht
 
 from magma.array import Array
@@ -23,14 +22,22 @@
 from magma.wire import wire
 
 
+def _make_bit_vector_t(width, init):
+    try:
+        import coreir
+    except ImportError:
+        return ht.BitVector[width](init)
+    return coreir.type.BitVector[width](init)
+
+
 class _CoreIRRegister(Generator):
     """
     Internally used generator for CoreIR register primitive
     """
     def __init__(self, width, init=0, has_async_reset=False,
                  has_async_resetn=False):
         self.name = "reg_P"
-        self.coreir_configargs = {"init": coreir.type.BitVector[width](init)}
+        self.coreir_configargs = {"init": _make_bit_vector_t(width, init)}
         T = Bits[width]
         self.io = IO(I=In(T), CLK=In(Clock), O=Out(T))
 
@@ -52,7 +59,7 @@ def __init__(self, width, init=0, has_async_reset=False,
 
         self.stateful = True
         self.primitive = True
-        self.default_kwargs = {"init": coreir.type.BitVector[width](init)}
+        self.default_kwargs = {"init": _make_bit_vector_t(width, init)}
         self.coreir_genargs = {"width": width}
         self.renamed_ports = coreir_port_mapping
 

magma/util.py

@@ -4,7 +4,6 @@
 from magma.tuple import Tuple
 from magma import clear_cachedFunctions
 
-from magma.frontend import coreir_
 from magma.generator import reset_generator_cache
 from magma.logging import flush_all
 from magma.when import reset_context as reset_when_context
@@ -54,7 +53,12 @@ def reset_global_context():
     compiler's state
     """
     clear_cachedFunctions()
-    coreir_.ResetCoreIR()
+    try:
+        from magma.frontend import coreir_
+    except ImportError:
+        pass
+    else:
+        coreir_.ResetCoreIR()
     reset_generator_cache()
     flush_all()  # flush all staged logs
     reset_when_context()

setup.py

@@ -39,7 +39,6 @@
         "pyverilog",
         "numpy",
         "graphviz",
-        "coreir>=2.0.151",
         "hwtypes>=1.4.4",
         "ast_tools>=0.0.16",
         "staticfg",

tests/gold/TopBasicAsserts_coreir-verilog.sv → tests/gold/TopBasicAsserts_coreirverilog.sv

@@ -4,7 +4,7 @@ module corebit_term (
 
 endmodule
 
-module TopBasicAsserts_coreir-verilog (
+module TopBasicAsserts_coreirverilog (
     input I,
     input O,
     input other
@@ -21,7 +21,7 @@ corebit_term corebit_term_inst2 (
 endmodule
 
 
-bind Top TopBasicAsserts_coreir-verilog TopBasicAsserts_coreir-verilog_inst (
+bind Top TopBasicAsserts_coreirverilog TopBasicAsserts_coreirverilog_inst (
     .I(I),
     .O(O),
     .other(_magma_bind_wire_0)

tests/gold/TopBasicAsserts_mlirverilog.sv

@@ -0,0 +1,14 @@
+module TopBasicAsserts_mlirverilog(
+  input I,
+        O,
+        other
+);
+
+endmodule
+
+
+bind Top TopBasicAsserts_mlirverilog TopBasicAsserts_mlirverilog_inst (
+    .I(I),
+    .O(O),
+    .other(_magma_bind_wire_0)
+);

tests/gold/TopXMRAsserts_coreir-verilog.sv → tests/gold/TopXMRAsserts_coreirverilog.sv

@@ -4,7 +4,7 @@ module corebit_term (
 
 endmodule
 
-module TopXMRAsserts_coreir-verilog (
+module TopXMRAsserts_coreirverilog (
     input I,
     input O,
     input other
@@ -21,7 +21,7 @@ corebit_term corebit_term_inst2 (
 endmodule
 
 
-bind Top TopXMRAsserts_coreir-verilog TopXMRAsserts_coreir-verilog_inst (
+bind Top TopXMRAsserts_coreirverilog TopXMRAsserts_coreirverilog_inst (
     .I(I),
     .O(O),
     .other(middle._magma_bind_wire_0)

tests/gold/TopXMRAsserts_mlirverilog.sv

@@ -0,0 +1,14 @@
+module TopXMRAsserts_mlirverilog(
+  input I,
+        O,
+        other
+);
+
+endmodule
+
+
+bind Top TopXMRAsserts_mlirverilog TopXMRAsserts_mlirverilog_inst (
+    .I(I),
+    .O(O),
+    .other(middle._magma_bind_wire_0)
+);

tests/gold/test_bind_basic_mlir-verilog.v

@@ -0,0 +1,9 @@
+module Top(
+  input  I,
+  output O
+);
+
+  wire _magma_bind_wire_0 = I;
+  assign O = I;
+endmodule
+

tests/gold/test_bind_xmr_mlir-verilog.v

@@ -0,0 +1,31 @@
+module Bottom(
+  input  I,
+  output O
+);
+
+  assign O = I;
+endmodule
+
+module Middle(
+  input  I,
+  output O
+);
+
+  wire _magma_bind_wire_0 = I;
+  Bottom bottom (
+    .I (I),
+    .O (O)
+  );
+endmodule
+
+module Top(
+  input  I,
+  output O
+);
+
+  Middle middle (
+    .I (I),
+    .O (O)
+  );
+endmodule
+

tests/test_circuit/gold/test_for_loop_def.json

@@ -17,33 +17,33 @@
         "instances":{
           "and2_0":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           },
           "and2_1":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           },
           "and2_2":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           },
           "and2_3":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           }
         },
         "connections":[
-          ["self.I.0","and2_0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"63"}],
-          ["self.I.1","and2_0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"64"}],
-          ["and2_1.I0","and2_0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
-          ["self.I.1","and2_1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}],
-          ["and2_2.I0","and2_1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
-          ["self.I.1","and2_2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}],
-          ["and2_3.I0","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
-          ["self.I.1","and2_3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}],
-          ["self.O","and2_3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"70"}]
+          ["self.I.0","and2_0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
+          ["self.I.1","and2_0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"63"}],
+          ["and2_1.I0","and2_0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
+          ["self.I.1","and2_1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
+          ["and2_2.I0","and2_1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
+          ["self.I.1","and2_2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
+          ["and2_3.I0","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
+          ["self.I.1","and2_3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
+          ["self.O","and2_3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"69"}]
         ],
-        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"}
+        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"55"}
       }
     }
   }

tests/test_circuit/gold/test_for_loop_def.v

@@ -1,30 +1,30 @@
-// Defined at tests/test_circuit/test_define.py:56
+// Defined at tests/test_circuit/test_define.py:55
 module main (input [1:0] I, output  O);
 wire  and2_0_O;
 wire  and2_1_O;
 wire  and2_2_O;
 wire  and2_3_O;
-// Instanced at tests/test_circuit/test_define.py:61
-// Argument I0(I[0]) wired at tests/test_circuit/test_define.py:63
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:64
-// Argument O(and2_0_O) wired at tests/test_circuit/test_define.py:66
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(I[0]) wired at tests/test_circuit/test_define.py:62
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:63
+// Argument O(and2_0_O) wired at tests/test_circuit/test_define.py:65
 And2 and2_0 (.I0(I[0]), .I1(I[1]), .O(and2_0_O));
-// Instanced at tests/test_circuit/test_define.py:61
-// Argument I0(and2_0_O) wired at tests/test_circuit/test_define.py:66
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:67
-// Argument O(and2_1_O) wired at tests/test_circuit/test_define.py:66
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(and2_0_O) wired at tests/test_circuit/test_define.py:65
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:66
+// Argument O(and2_1_O) wired at tests/test_circuit/test_define.py:65
 And2 and2_1 (.I0(and2_0_O), .I1(I[1]), .O(and2_1_O));
-// Instanced at tests/test_circuit/test_define.py:61
-// Argument I0(and2_1_O) wired at tests/test_circuit/test_define.py:66
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:67
-// Argument O(and2_2_O) wired at tests/test_circuit/test_define.py:66
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(and2_1_O) wired at tests/test_circuit/test_define.py:65
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:66
+// Argument O(and2_2_O) wired at tests/test_circuit/test_define.py:65
 And2 and2_2 (.I0(and2_1_O), .I1(I[1]), .O(and2_2_O));
-// Instanced at tests/test_circuit/test_define.py:61
-// Argument I0(and2_2_O) wired at tests/test_circuit/test_define.py:66
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:67
-// Argument O(and2_3_O) wired at tests/test_circuit/test_define.py:70
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(and2_2_O) wired at tests/test_circuit/test_define.py:65
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:66
+// Argument O(and2_3_O) wired at tests/test_circuit/test_define.py:69
 And2 and2_3 (.I0(and2_2_O), .I1(I[1]), .O(and2_3_O));
-// Wired at tests/test_circuit/test_define.py:70
+// Wired at tests/test_circuit/test_define.py:69
 assign O = and2_3_O;
 endmodule
 

tests/test_circuit/gold/test_interleaved_instance_wiring.json

@@ -17,27 +17,27 @@
         "instances":{
           "and2_0":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"89"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"88"}
           },
           "and2_1":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"90"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"89"}
           },
           "and2_2":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"96"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"95"}
           }
         },
         "connections":[
-          ["self.I.0","and2_0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"92"}],
-          ["self.I.1","and2_0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"93"}],
-          ["and2_1.I0","and2_0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"94"}],
-          ["self.I.1","and2_1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"95"}],
-          ["and2_2.I0","and2_1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"97"}],
-          ["self.I.0","and2_2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"98"}],
-          ["self.O","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"100"}]
+          ["self.I.0","and2_0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"91"}],
+          ["self.I.1","and2_0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"92"}],
+          ["and2_1.I0","and2_0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"93"}],
+          ["self.I.1","and2_1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"94"}],
+          ["and2_2.I0","and2_1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"96"}],
+          ["self.I.0","and2_2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"97"}],
+          ["self.O","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"99"}]
         ],
-        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"86"}
+        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"85"}
       }
     }
   }