Merge pull request #1066 from phanrahan/mlir-add-disable-initial-bloc…

…ks-option [MLIR] Add disable_initial_blocks option
phanrahan · May 3, 2022 · 768a4ca · 768a4ca
2 parents 55e250b + f03187a
commit 768a4ca
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Showing 7 changed files with 112 additions and 4 deletions.
diff --git a/magma/backend/mlir/compile_to_mlir_opts.py b/magma/backend/mlir/compile_to_mlir_opts.py
@@ -9,3 +9,4 @@ class CompileToMlirOpts:
     use_native_bind_processor: bool = False
     verilog_prefix: Optional[str] = None
     user_namespace: Optional[str] = None
+    disable_initial_blocks: bool = False
diff --git a/magma/backend/mlir/hardware_module.py b/magma/backend/mlir/hardware_module.py
@@ -284,8 +284,9 @@ def visit_coreir_reg(self, module: ModuleWrapper) -> bool:
             always.operands.append(module.operands[1])
             with push_block(always.reset_block):
                 sv.PAssignOp(operands=[reg, const])
-        with push_block(sv.InitialOp()):
-            sv.BPAssignOp(operands=[reg, const])
+        if not self._ctx.opts.disable_initial_blocks:
+            with push_block(sv.InitialOp()):
+                sv.BPAssignOp(operands=[reg, const])
         sv.ReadInOutOp(operands=[reg], results=module.results.copy())
         return True
 
@@ -518,8 +519,9 @@ def make_register(T, data, init, result):
             if has_reset:
                 with push_block(always.reset_block):
                     sv.PAssignOp(operands=[reg, const])
-            with push_block(sv.InitialOp()):
-                sv.BPAssignOp(operands=[reg, const])
+            if not self._ctx.opts.disable_initial_blocks:
+                with push_block(sv.InitialOp()):
+                    sv.BPAssignOp(operands=[reg, const])
             sv.ReadInOutOp(operands=[reg], results=[result])
 
         inst = module.module

diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper_disable_initial_blocks.mlir b/tests/test_backend/test_mlir/golds/complex_register_wrapper_disable_initial_blocks.mlir
@@ -0,0 +1,37 @@
+hw.module @complex_register_wrapper(%a: !hw.struct<x: i8, y: i1>, %b: !hw.array<6xi16>, %CLK: i1, %CE: i1, %ASYNCRESET: i1) -> (y: !hw.struct<u: !hw.struct<x: i8, y: i1>, v: !hw.array<6xi16>>) {
+    %1 = sv.reg {name = "Register_inst0"} : !hw.inout<!hw.struct<x: i8, y: i1>>
+    sv.alwaysff(posedge %CLK) {
+        sv.if %CE {
+            sv.passign %1, %a : !hw.struct<x: i8, y: i1>
+        }
+    } (asyncreset : posedge %ASYNCRESET) {
+        sv.passign %1, %2 : !hw.struct<x: i8, y: i1>
+    }
+    %3 = hw.constant 10 : i8
+    %4 = hw.constant 1 : i1
+    %2 = hw.struct_create (%3, %4) : !hw.struct<x: i8, y: i1>
+    %0 = sv.read_inout %1 : !hw.inout<!hw.struct<x: i8, y: i1>>
+    %6 = sv.reg {name = "Register_inst1"} : !hw.inout<!hw.array<6xi16>>
+    sv.alwaysff(posedge %CLK) {
+        sv.passign %6, %b : !hw.array<6xi16>
+    }
+    %8 = hw.constant 0 : i16
+    %9 = hw.constant 2 : i16
+    %10 = hw.constant 4 : i16
+    %11 = hw.constant 6 : i16
+    %12 = hw.constant 8 : i16
+    %13 = hw.constant 10 : i16
+    %7 = hw.array_create %8, %9, %10, %11, %12, %13 : i16
+    %5 = sv.read_inout %6 : !hw.inout<!hw.array<6xi16>>
+    %14 = hw.struct_create (%0, %5) : !hw.struct<u: !hw.struct<x: i8, y: i1>, v: !hw.array<6xi16>>
+    %15 = hw.struct_extract %a["x"] : !hw.struct<x: i8, y: i1>
+    %17 = sv.reg {name = "Register_inst2"} : !hw.inout<i8>
+    sv.alwaysff(posedge %CLK) {
+        sv.if %CE {
+            sv.passign %17, %15 : i8
+        }
+    }
+    %18 = hw.constant 0 : i8
+    %16 = sv.read_inout %17 : !hw.inout<i8>
+    hw.output %14 : !hw.struct<u: !hw.struct<x: i8, y: i1>, v: !hw.array<6xi16>>
+}
diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper_disable_initial_blocks.v b/tests/test_backend/test_mlir/golds/complex_register_wrapper_disable_initial_blocks.v
@@ -0,0 +1,31 @@
+module complex_register_wrapper(	// <stdin>:1:1
+  input  struct packed {logic [7:0] x; logic y; }                                          a,
+  input  [5:0][15:0]                                                                       b,
+  input                                                                                    CLK,
+  input                                                                                    CE,
+  input                                                                                    ASYNCRESET,
+  output struct packed {struct packed {logic [7:0] x; logic y; } u; logic [5:0][15:0] v; } y);
+
+     struct packed {logic [7:0] x; logic y; } Register_inst0;	// <stdin>:2:10
+  reg [5:0][15:0]                              Register_inst1;	// <stdin>:14:10
+  reg [7:0]                                    Register_inst2;	// <stdin>:28:11
+
+  always_ff @(posedge CLK or posedge ASYNCRESET) begin	// <stdin>:3:5
+    if (ASYNCRESET) begin	// <stdin>:3:5
+      automatic struct packed {logic [7:0] x; logic y; } _T = '{x: (8'hA), y: (1'h1)};	// <stdin>:10:10, :11:10, :12:10
+
+      Register_inst0 <= _T;	// <stdin>:8:9
+    end
+    else begin	// <stdin>:3:5
+      if (CE)	// <stdin>:4:9
+        Register_inst0 <= a;	// <stdin>:5:13
+    end
+  end // always_ff @(posedge or posedge)
+  always_ff @(posedge CLK) begin	// <stdin>:29:5
+    Register_inst1 <= b;	// <stdin>:16:9
+    if (CE)	// <stdin>:30:9
+      Register_inst2 <= a.x;	// <stdin>:27:11, :31:13
+  end // always_ff @(posedge)
+  assign y = '{u: Register_inst0, v: Register_inst1};	// <stdin>:13:10, :25:10, :26:11, :36:5
+endmodule
+
diff --git a/tests/test_backend/test_mlir/golds/simple_register_wrapper_disable_initial_blocks.mlir b/tests/test_backend/test_mlir/golds/simple_register_wrapper_disable_initial_blocks.mlir
@@ -0,0 +1,9 @@
+hw.module @simple_register_wrapper(%a: i8, %CLK: i1) -> (y: i8) {
+    %1 = sv.reg {name = "reg0"} : !hw.inout<i8>
+    sv.alwaysff(posedge %CLK) {
+        sv.passign %1, %a : i8
+    }
+    %2 = hw.constant 3 : i8
+    %0 = sv.read_inout %1 : !hw.inout<i8>
+    hw.output %0 : i8
+}
diff --git a/tests/test_backend/test_mlir/golds/simple_register_wrapper_disable_initial_blocks.v b/tests/test_backend/test_mlir/golds/simple_register_wrapper_disable_initial_blocks.v
@@ -0,0 +1,12 @@
+module simple_register_wrapper(	// <stdin>:1:1
+  input  [7:0] a,
+  input        CLK,
+  output [7:0] y);
+
+  reg [7:0] reg0;	// <stdin>:2:10
+
+  always_ff @(posedge CLK)	// <stdin>:3:5
+    reg0 <= a;	// <stdin>:4:9
+  assign y = reg0;	// <stdin>:7:10, :8:5
+endmodule
+
diff --git a/tests/test_backend/test_mlir/test_compile_to_mlir_local_examples.py b/tests/test_backend/test_mlir/test_compile_to_mlir_local_examples.py
@@ -6,6 +6,7 @@
 from examples import (
     simple_aggregates_product, aggregate_mux_wrapper, complex_register_wrapper,
     complex_bind, simple_comb,
+    simple_register_wrapper,
 )
 from test_utils import get_local_examples, run_test_compile_to_mlir
 
@@ -53,3 +54,18 @@ def test_compile_to_mlir_verilog_prefix(ckt):
         "gold_name": f"{ckt.name}_verilog_prefix",
     }
     run_test_compile_to_mlir(ckt, **kwargs)
+
+
+@pytest.mark.parametrize(
+    "ckt",
+    [
+        simple_register_wrapper,
+        complex_register_wrapper,
+    ]
+)
+def test_compile_to_mlir_disable_initial_blocks(ckt):
+    kwargs = {
+        "disable_initial_blocks": True,
+        "gold_name": f"{ckt.name}_disable_initial_blocks",
+    }
+    run_test_compile_to_mlir(ckt, **kwargs)