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[Examples] Add swap test/logic
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leonardt committed Mar 13, 2024
1 parent 677f240 commit f44d3d2
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Showing 5 changed files with 31 additions and 2 deletions.
8 changes: 8 additions & 0 deletions examples/even_odd_sort.py
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@@ -0,0 +1,8 @@
import magma as m


class Swap(m.Circuit):
io = m.IO(I=m.In(m.Bits[2]), O=m.Out(m.Bits[2]))
# io.O @= m.bits([io.I.reduce_and(), io.I.reduce_or())
print(m.fork(m.Bit.And, m.Bit.Or))
io.O @= m.uncurry(m.fork(m.Bit.And(), m.Bit.Or()))(io.I)
17 changes: 17 additions & 0 deletions examples/tests/test_even_odd_sort.py
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import fault as f
from ..even_odd_sort import Swap
from hwtypes import BitVector


def swap(I: BitVector[2]):
return BitVector[2]([I[0] & I[1], I[0] | I[1]])


def test_swap():
tester = f.Tester(Swap)
for i in range(2):
for j in range(2):
tester.circuit.I = I = BitVector[2]([i, j])
tester.eval()
tester.circuit.O.expect(swap(I))
tester.compile_and_run('verilator', magma_output="mlir-verilog")
5 changes: 3 additions & 2 deletions magma/bit.py
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Expand Up @@ -94,7 +94,8 @@ def __ne__(self, other):
@magma_helper_function
@bit_cast
def __and__(self, other):
return type(self).undirected_t._declare_binary_op("and")()(self, other)
return self.And()(self, other)


@magma_helper_function
@bit_cast
Expand All @@ -104,7 +105,7 @@ def __rand__(self, other):
@magma_helper_function
@bit_cast
def __or__(self, other):
return type(self).undirected_t._declare_binary_op("or")()(self, other)
return self.Or()(self, other)

@magma_helper_function
@bit_cast
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2 changes: 2 additions & 0 deletions magma/bit_primitives.py
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Expand Up @@ -70,6 +70,8 @@ def simulate(self, value_store, state_store):
# NOTE(leonardt): Monkey patched functions.
Bit._declare_unary_op = _declare_unary_op
Bit._declare_binary_op = _declare_binary_op
Bit.And = Bit._declare_binary_op("and")
Bit.Or = Bit._declare_binary_op("or")


def make_Define(_name, port, direction):
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1 change: 1 addition & 0 deletions magma/braid.py
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Expand Up @@ -311,6 +311,7 @@ def uncurry(circuit, prefix='I'):
otherargs = []
uncurryargs = []
for name, port in circuit.interface.ports.items():
print(port.driven(), name)
# should we insert the argument in the position of the first match?
if not port.driven() and name.startswith(prefix) and \
circuit.interface.is_input(port):
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