Get inst verilog

[leonardt]

Here's a minimum example test setup for using the symbol table to refer to magma symbols from an imported magma generated verilog definition.

Here's a sketch of how we could support this:

1. Add API/logic to define_from_verilog using a symbol table. We can use the symbol table to reconstruct the original magma types (this would deprecate the old type_map interface, but also improve it because we could automatically add a wrapper to handle "repacking" tuples/arrays that have been flattened).
2. Add API to reference instances (possibly hierarchically) using string names. This could work for non-verilog circuits too, which would be nice for making things standard. For verilog imported circuits that have a symbol table, we can resolve the references and provide a "view" of the nested instance that should have the original magma types.
3. Update inline_verilog to support code generation using these "views" (can use verilog's cross module reference syntax)