Merge branch 'release/v2.0.0'

.github/FUNDING.yml

@@ -0,0 +1 @@
+custom: https://platformio.org/donate

.github/workflows/examples.yml

@@ -0,0 +1,35 @@
+name: Examples
+
+on: [push, pull_request]
+
+jobs:
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        os: [ubuntu-latest, windows-latest, macos-latest]
+        python-version: [3.7]
+        example:
+          - "examples/anymcu-blink"
+          - "examples/anymcu-header"
+          - "examples/assembly-blink"
+          - "examples/native-blink"
+          - "examples/stc-blink"
+          - "examples/stc-header"
+    runs-on: ${{ matrix.os }}
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: "recursive"
+      - name: Set up Python ${{ matrix.python-version }}
+        uses: actions/setup-python@v3
+        with:
+          python-version: ${{ matrix.python-version }}
+      - name: Install dependencies
+        run: |
+          python -m pip install --upgrade pip
+          pip install -U https://github.com/platformio/platformio/archive/develop.zip
+          pio pkg install --global --platform symlink://.
+      - name: Build examples
+        run: |
+          platformio run -d ${{ matrix.example }}

README.md

@@ -1,16 +1,15 @@
 # Intel MCS-51 (8051): development platform for [PlatformIO](http://platformio.org)
-[![Build Status](https://travis-ci.org/platformio/platform-intel_mcs51.svg?branch=develop)](https://travis-ci.org/platformio/platform-intel_mcs51)
-[![Build status](https://ci.appveyor.com/api/projects/status/0207sb475heyoaxa/branch/develop?svg=true)](https://ci.appveyor.com/project/ivankravets/platform-intel-mcs51/branch/develop)
+[![Build Status](https://github.com/platformio/platform-intel_mcs51/workflows/Examples/badge.svg)](https://github.com/platformio/platform-intel_mcs51/actions)
 
 The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex instruction set computer (CISC) instruction set, single chip microcontroller (µC) series developed by Intel in 1980 for use in embedded systems.
 
-* [Home](http://platformio.org/platforms/intel_mcs51) (home page in PlatformIO Registry)
-* [Documentation](http://docs.platformio.org/page/platforms/intel_mcs51.html) (advanced usage, packages, boards, frameworks, etc.)
+* [Home](https://registry.platformio.org/platforms/platformio/intel_mcs51) (home page in PlatformIO Registry)
+* [Documentation](https://docs.platformio.org/page/platforms/intel_mcs51.html) (advanced usage, packages, boards, frameworks, etc.)
 
 # Usage
 
 1. [Install PlatformIO](http://platformio.org)
-2. Create PlatformIO project and configure a platform option in [platformio.ini](http://docs.platformio.org/page/projectconf.html) file:
+2. Create PlatformIO project and configure a platform option in [platformio.ini](https://docs.platformio.org/page/projectconf.html) file:
 
 ## Stable version
 
@@ -32,4 +31,4 @@ board = ...
 
 # Configuration
 
-Please navigate to [documentation](http://docs.platformio.org/page/platforms/intel_mcs51.html).
+Please navigate to [documentation](https://docs.platformio.org/page/platforms/intel_mcs51.html).

boards/AT89S51.json

@@ -0,0 +1,27 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DAT89S51 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_AT89S51",
+    "f_cpu": "11059200L",
+    "size_iram": 128,
+    "size_xram": 0,
+    "size_code": 4096,
+    "size_heap": 64,
+    "mcu": "at89s51",
+    "cpu": "mcs51"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 128,
+    "maximum_size": 4096,
+    "protocol": "avrdude",
+    "avrdude_protocol": "AT89S51",
+    "protocols": [
+      "usbasp",
+	  "avrisp"
+    ]
+  },
+  "name": "Generic AT89S51",
+  "url": "https://www.microchip.com/wwwproducts/en/AT89S51",
+  "vendor": "Microchip & Atmel"
+}

boards/AT89S52.json

@@ -0,0 +1,27 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DAT89S52 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_AT89S52",
+    "f_cpu": "11059200L",
+    "size_iram": 256,
+    "size_xram": 0,
+    "size_code": 8192,
+    "size_heap": 64,
+    "mcu": "at89s52",
+    "cpu": "mcs51"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 256,
+    "maximum_size": 8192,
+    "protocol": "avrdude",
+    "avrdude_protocol": "AT89S52",
+    "protocols": [
+      "usbasp",
+	  "avrisp"
+    ]
+  },
+  "name": "Generic AT89S52",
+  "url": "https://www.microchip.com/wwwproducts/en/AT89S52",
+  "vendor": "Microchip & Atmel"
+}

boards/CH559.json

@@ -0,0 +1,20 @@
+{
+  "build": {
+    "f_cpu": "12000000L",
+    "size_iram": 256,
+    "size_xram": 6144,
+    "size_code": 65536,
+    "size_heap": 128,
+    "mcu": "ch559",
+    "cpu": "mcs51"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 6400,
+    "maximum_size": 65536,
+    "protocol": "ch55x"
+  },
+  "name": "CH559",
+  "url": "http://www.wch-ic.com/products/CH559.html",
+  "vendor": "WCH"
+}

boards/Generic8051.json

@@ -0,0 +1,21 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DGeneric8051 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_Generic8051",
+    "f_cpu": "11059200L",
+    "size_iram": 128,
+    "size_xram": 0,
+    "size_code": 4096,
+    "size_heap": 64,
+    "mcu": "8051",
+    "cpu": "mcs51"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 128,
+    "maximum_size": 4096
+  },
+  "name": "Generic 8051",
+  "url": "https://en.wikipedia.org/wiki/Intel_8051",
+  "vendor": "Intel & Licensees"
+}

boards/Generic8052.json

@@ -0,0 +1,21 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DGeneric8052 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_Generic8052",
+    "f_cpu": "11059200L",
+    "size_iram": 256,
+    "size_xram": 0,
+    "size_code": 8192,
+    "size_heap": 64,
+    "mcu": "8052",
+    "cpu": "mcs51"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 256,
+    "maximum_size": 8192
+  },
+  "name": "Generic 8052",
+  "url": "https://en.wikipedia.org/wiki/Intel_8051",
+  "vendor": "Intel & licensees"
+}

boards/IAP12C5A62S2.json

@@ -0,0 +1,27 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DSTC12C5AXXS2 -DIAP12C5A62S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2",
+    "f_cpu": "11059200L",
+    "size_iram": 256,
+    "size_xram": 1024,
+    "size_code": 63488,
+	"size_heap": 128,
+    "mcu": "iap12c5a62s2",
+    "cpu": "mcs51",
+    "variant": "stc12c5axxS2"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 1280,
+    "maximum_size": 63488,
+    "protocol": "stcgal",
+    "stcgal_protocol": "stc12",
+    "protocols": [
+      "stcgal"
+    ]
+  },
+  "name": "Generic IAP12C5A62S2",
+  "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html",
+  "vendor": "STC"
+}

boards/IAP15F106.json

@@ -0,0 +1,27 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DSTC15F10X -DIAP15F106 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X",
+    "f_cpu": "11059200L",
+    "size_iram": 128,
+    "size_xram": 0,
+    "size_code": 6144,
+    "size_heap": 64,
+    "mcu": "iap15f106",
+    "cpu": "mcs51",
+    "variant": "stc15f10x"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 128,
+    "maximum_size": 6144,
+    "protocol": "stcgal",
+    "stcgal_protocol": "stc15",
+    "protocols": [
+      "stcgal"
+    ]
+  },
+  "name": "Generic IAP15F106",
+  "url": "http://www.stcmicro.com/STC/STC15F100.html",
+  "vendor": "STC"
+}

boards/IAP15F206A.json

@@ -0,0 +1,27 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DSTC15F20XA -DIAP15F206A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA",
+    "f_cpu": "11059200L",
+    "size_iram": 256,
+    "size_xram": 0,
+    "size_code": 6144,
+    "size_heap": 64,
+    "mcu": "iap15f206a",
+    "cpu": "mcs51",
+    "variant": "stc15f20xa"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 256,
+    "maximum_size": 6144,
+    "protocol": "stcgal",
+    "stcgal_protocol": "stc15",
+    "protocols": [
+      "stcgal"
+    ]
+  },
+  "name": "Generic IAP15F206A",
+  "url": "https://www.stcmicro.com/STC/STC15F204EA.html",
+  "vendor": "STC"
+}

boards/IAP15F2K61S.json

@@ -0,0 +1,27 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DSTC15F2KXXS -DIAP15F2K61S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS",
+    "f_cpu": "11059200L",
+    "size_iram": 256,
+    "size_xram": 1792,
+    "size_code": 62464,
+    "size_heap": 128,
+    "mcu": "iap15f2k61s",
+    "cpu": "mcs51",
+    "variant": "stc15f2kxxs"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 2048,
+    "maximum_size": 62464,
+    "protocol": "stcgal",
+    "stcgal_protocol": "stc15",
+    "protocols": [
+      "stcgal"
+    ]
+  },
+  "name": "Generic IAP15F2K61S",
+  "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html",
+  "vendor": "STC"
+}

boards/IAP15F2K61S2.json

@@ -0,0 +1,27 @@
+{
+  "build": {
+    "core": "naked",
+    "extra_flags": "-DSTC15F2KXXS2 -DIAP15F2K61S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2",
+    "f_cpu": "11059200L",
+    "size_iram": 256,
+    "size_xram": 1792,
+    "size_code": 62464,
+    "size_heap": 128,
+    "mcu": "iap15f2k61s2",
+    "cpu": "mcs51",
+    "variant": "stc15f2kxxs2"
+  },
+  "frameworks": [],
+  "upload": {
+    "maximum_ram_size": 2048,
+    "maximum_size": 62464,
+    "protocol": "stcgal",
+    "stcgal_protocol": "stc15",
+    "protocols": [
+      "stcgal"
+    ]
+  },
+  "name": "Generic IAP15F2K61S2",
+  "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html",
+  "vendor": "STC"
+}