init submodules #4
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May 9, 2022 18:44
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commit dfd6063 Author: melonedo <44501064+melonedo@users.noreply.github.com> Date: Sat Aug 27 18:32:37 2022 +0800 gollvm: pass arch info to the integrated assembler (plctlab#27) Currently, architecture information is passed to the compiler but not the integrated assembler, causing discrepancies in the ABI chosen by the two tools, especially on the RISC-V platform. This patch makes sure both share the same architecture information. Change-Id: I29f441e86e06f1f0b46c3ea62576a7d1291c2ce4 Co-authored-by: melonedo <funanzeng@gmail.com> commit 63e7226 Merge: 9f4a919 c52da0c Author: ChunyuLiao <liaochunyu126@126.com> Date: Wed Aug 24 08:25:11 2022 +0800 Merge pull request plctlab#26 from realqhc/gollvm-build-riscv Address Than's review on crosscompile, add readme commit c52da0c Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Wed Aug 24 07:29:22 2022 +1000 fix readme Change-Id: Id262558c40aa8ec008814159f355b77039987452 commit 2cf9713 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Wed Aug 24 07:08:54 2022 +1000 fix gopackage simplify logic reduce redundant code, add new section crosscompile in readme, redo the LinuxToolChain.cpp edit so it correctly detects all relevant folders without any issue Change-Id: Ia047b486f9b51713ae1c1786ea80d409a57974ca commit 9f4a919 Merge: 9225954 6ad1234 Author: ChunyuLiao <liaochunyu126@126.com> Date: Wed Aug 17 14:31:06 2022 +0800 Merge pull request plctlab#24 from realqhc/gollvm-build-riscv Try fix undefined reference to `__atomic_fetch_and_1' for check_libgo_runtime_pprof commit 6ad1234 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Wed Aug 17 16:21:38 2022 +1000 remove pthread Change-Id: I1e6b10a439bca0809a17d4b24b9a9f44939e572c commit f796915 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Wed Aug 17 05:33:05 2022 +1000 add atomic and pthread when building libgo Change-Id: I5d43866eebf8015b4a29a8f783fab245eabf20b3 commit 9225954 Merge: db78b92 2a081e8 Author: ChunyuLiao <liaochunyu126@126.com> Date: Sun Aug 14 18:41:17 2022 +0800 Merge pull request plctlab#23 from realqhc/gollvm-build-riscv regenerate ArchCpusAttr by updated clang commit 2a081e8 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Sun Aug 14 19:26:17 2022 +1000 regenerate ArchCpusAttr by updated clang Change-Id: If8595f470de6a1ff4b08de29b77f37ac0f916c28 commit db78b92 Merge: 8bbaf19 5c3c182 Author: ChunyuLiao <liaochunyu126@126.com> Date: Sat Aug 13 20:23:04 2022 +0800 Merge pull request plctlab#22 from melonedo/pr22 Set up arch info for integrated assembler commit 5c3c182 Author: melonedo <funanzeng@gmail.com> Date: Sat Aug 13 17:36:12 2022 +0800 Set up arch info for integrated assembler commit 8bbaf19 Merge: 986ac1c 2db9085 Author: ChunyuLiao <liaochunyu126@126.com> Date: Sun Aug 7 19:58:12 2022 +0800 Merge pull request plctlab#21 from melonedo/pr21 Enable check_xxx_tool tests commit 2db9085 Author: melonedo <funanzeng@gmail.com> Date: Sun Aug 7 12:23:18 2022 +0800 Enable check_xxx_tool tests Change-Id: I953e7d83e69d728724f963ae9004cd549a1e3883 commit 986ac1c Merge: 1acdde4 b901510 Author: ChunyuLiao <liaochunyu126@126.com> Date: Sat Aug 6 18:37:08 2022 +0800 Merge pull request plctlab#20 from realqhc/gollvm-build-riscv sync with main? commit b901510 Merge: 1acdde4 9de48d3 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Fri Aug 5 21:14:37 2022 +1000 Merge branch 'master' into gollvm-build-riscv-upstream Change-Id: Ied5d990cca4a117fbc09875ad4a7b26684f5589e commit 1acdde4 Author: melonedo <44501064+melonedo@users.noreply.github.com> Date: Tue Jul 26 21:24:43 2022 +0800 Gollvm build riscv (plctlab#19) * Apply GoSafeGetgPass on RISC-V * Force -funwind-tables on LibffiUtils Co-authored-by: melonedo <funanzeng@gmail.com> commit a5cf77d Author: melonedo <44501064+melonedo@users.noreply.github.com> Date: Tue Jul 26 14:08:15 2022 +0800 Apply GoSafeGetgPass on RISC-V (plctlab#18) Co-authored-by: melonedo <funanzeng@gmail.com> commit 121b2ae Author: realqhc <98016705+realqhc@users.noreply.github.com> Date: Tue Jul 12 20:54:14 2022 +1000 fix space in -funwind-tables (plctlab#15) Change-Id: Id1b24b28a3d0b7a1645a39c491af9c8352587d82 commit f5a8432 Merge: 181e68e 8538af9 Author: ChunyuLiao <liaochunyu126@126.com> Date: Tue Jul 12 16:24:43 2022 +0800 Merge pull request plctlab#13 from realqhc/gollvm-build-riscv fix -funwind-tables by including it in LibbacktraceUtils. commit 8538af9 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Tue Jul 12 16:11:12 2022 +1000 fix -funwind-tables by including it in LibbacktraceUtils. Change-Id: If0d6e1bb744431f3f6b4dae1593a0604c36d533f commit 181e68e Merge: e3b80a8 3e23627 Author: ChunyuLiao <liaochunyu126@126.com> Date: Tue Jul 12 16:09:30 2022 +0800 Merge pull request plctlab#11 from melonedo/gollvm-build-riscv Support calling objdump not on path and add spaces around -funwind-tables commit 3e23627 Author: melonedo <funanzeng@gmail.com> Date: Tue Jul 12 14:53:29 2022 +0800 Support calling objdump not on path and add spaces around -funwind-tables commit e3b80a8 Merge: ad3a521 68adf7c Author: ChunyuLiao <liaochunyu126@126.com> Date: Mon Jul 11 20:37:19 2022 +0800 Merge pull request plctlab#10 from realqhc/gollvm-build-riscv allow build on rv64gc commit 68adf7c Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Mon Jul 11 19:53:08 2022 +1000 add -funwind-tables for rv64 credit:@melonedo Change-Id: Ie5ff83974f7a662d3e09a490aa894f0e92637e32 commit 967716a Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Mon Jul 11 11:47:13 2022 +1000 update libbacktrace and libffi cmake to try fix riscv backtrace Change-Id: I3dcaafd6e42ae5ac90a50744df80c815f378d06c commit 12761ce Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Fri Jul 1 00:05:35 2022 +1000 try fix rvcabi Change-Id: Ib045fee4b4bc369d72f429e86e5c58c909f31570 commit 0fef5b3 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Fri Jun 24 06:09:40 2022 +1000 allow crosscompile and link to risc-v Change-Id: Ie18b580cbe4b8c2ca8274d41f60e5a8db2a7b5d2 commit c486b70 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Thu Jun 23 20:06:00 2022 +1000 fix inclusion of cpu_gccgo_x86 for amd64 Change-Id: I9ee273e1766cf65df6f4ace32b01d23a2ef3c770 commit 6781059 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Thu Jun 23 19:46:30 2022 +1000 allow crosscompile for libgmp libmpfr and libmpc Change-Id: I7cb652d885ed41906241879f3a4f8844fadeeba0 commit aa44318 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Thu Jun 23 17:20:09 2022 +1000 stop including cpu_gccgo_x86.c for RISC-V Change-Id: I49a4597e08906d468314baaf469a59e3b379e712 commit ab88092 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Thu Jun 23 13:42:49 2022 +1000 add riscv build proprties to aeshash.c Change-Id: I8de3b543660edff6a03795d258a424b1c3be79c4 commit c35a013 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Thu Jun 23 00:14:57 2022 +1000 update libffi target Change-Id: I726e88d78b517a36e566e498fd605a3eacd8d1cd commit 8b6f329 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Mon Jun 6 21:58:21 2022 +1000 add cmake stuff for build on riscv Change-Id: Icdea45ef8623371b5141eb03b42c231854ad1f23 commit cedad32 Merge: 59f1f5d 0f0f9c6 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Mon Jun 6 21:41:42 2022 +1000 Merge branch 'master' into gollvm-build-riscv Change-Id: Id7a9bb60b36241f1fd98fb1e13058efe41f40aa1 commit 59f1f5d Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Mon Jun 6 21:40:29 2022 +1000 add cmake stuff for build on riscv Change-Id: I5fbba16e8e45926f2bffc1f17ccca4f9713f9d3e commit 8bdf08f Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Wed May 25 12:44:30 2022 +1000 add some more tests for cabioracle Change-Id: I3b3391046000b2b908c8dbd657f76e44054d0101 commit b19c7e1 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Tue May 24 23:10:51 2022 +1000 remove "unsupported calling convention" error Change-Id: Ided89d4e797d443242ec3ca227595f945bb73d28 commit 80f2543 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Tue May 24 22:44:59 2022 +1000 add a unit test (need to be tested on real machine), fix float issues Change-Id: Iba5040379c6233672e1670ebdaa7200e794c2db1 commit 091a1e2 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Tue May 24 21:28:53 2022 +1000 add assertion message Change-Id: I7a7a370ef8f065a90f98bf83044cdc3b8ca4ec4f commit 85780ea Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Tue May 24 19:54:13 2022 +1000 fix unsupported error message Change-Id: Ic9ada21c3689d2fc9e63d3c425b906f4cfd43f38 commit e65f068 Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Sun May 22 19:11:19 2022 +1000 remove repeated definition of riscv cabi Change-Id: Ia2be82030b194d799eaf063ac925d37db36b1b43 commit 71e6a0e Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Sun May 22 18:57:37 2022 +1000 luxvfan crosscompile Change-Id: Id5696e9d827464c0bb572b56c0d25ce8da5b65e7 commit b11997a Author: Qihan Cai <qcai8733@uni.sydney.edu.au> Date: Tue May 17 19:33:50 2022 +1000 initial riscv cabi Change-Id: Id4bf54bb8da5cb3b98769809ad316f14101b0ff1 commit ad3a521 Merge: 306888c 22c8003 Author: Shao-Ce SUN <sunshaoce@iscas.ac.cn> Date: Mon May 9 18:59:44 2022 +0800 Merge pull request plctlab#4 from sunshaoce/master init submodules commit 22c8003 Author: Shao-Ce SUN <sunshaoce@iscas.ac.cn> Date: Mon May 9 18:44:38 2022 +0800 add modules commit 000c335 Author: Shao-Ce SUN <sunshaoce@iscas.ac.cn> Date: Mon May 9 18:44:03 2022 +0800 add submodules commit 306888c Merge: 0e34e09 e1c6240 Author: Shao-Ce SUN <sunshaoce@iscas.ac.cn> Date: Mon May 9 16:51:14 2022 +0800 Merge pull request #1 from sunshaoce/master Create .gitmodules commit e1c6240 Author: Shao-Ce SUN <sunshaoce@iscas.ac.cn> Date: Sat May 7 14:34:21 2022 +0800 Create .gitmodules Change-Id: I51ef0fecc3ee36af4c9dfa12e89e6e75be80ffe1
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