MSS config: update LPDDR4 tRFC value

Updated the tRFC value for LPDDR4 from 380ns to 280ns to match the LPDDR4 data sheet and regenerated XML files using Libero SoC v2023.2. Signed-off-by: M31864 <Hugh.Breslin@microchip.com>
polarfire-soc · Jan 8, 2024 · 61c4ba9 · 61c4ba9
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Showing 8 changed files with 1,229 additions and 59 deletions.
diff --git a/XML/MPFS_Icicle_MSS_Baremetal.xml b/XML/MPFS_Icicle_MSS_Baremetal.xml
diff --git a/XML/MPFS_Icicle_MSS_Baremetal_I2C_Loopback.xml b/XML/MPFS_Icicle_MSS_Baremetal_I2C_Loopback.xml
diff --git a/XML/MPFS_Icicle_MSS_Baremetal_SPI_Loopback.xml b/XML/MPFS_Icicle_MSS_Baremetal_SPI_Loopback.xml
diff --git a/XML/MPFS_Icicle_MSS_Linux_I2C_Loopback_cfg.xml b/XML/MPFS_Icicle_MSS_Linux_I2C_Loopback_cfg.xml
diff --git a/XML/MPFS_Icicle_MSS_Linux_SPI_Loopback_cfg.xml b/XML/MPFS_Icicle_MSS_Linux_SPI_Loopback_cfg.xml
diff --git a/XML/MPFS_Icicle_MSS_Linux_cfg.xml b/XML/MPFS_Icicle_MSS_Linux_cfg.xml
diff --git a/script_support/MPFS_ICICLE_MSS_baremetal.cfg b/script_support/MPFS_ICICLE_MSS_baremetal.cfg
@@ -1012,7 +1012,7 @@ LPDDR4_TIMING_RAS                                   42
 LPDDR4_TIMING_RC                                    63
 LPDDR4_TIMING_RCD                                   18
 LPDDR4_TIMING_REFI                                  3.905
-LPDDR4_TIMING_RFC                                   380
+LPDDR4_TIMING_RFC                                   280
 LPDDR4_TIMING_RP                                    21
 LPDDR4_TIMING_RRD                                   10
 LPDDR4_TIMING_RTP                                   10

diff --git a/script_support/MPFS_ICICLE_MSS_linux.cfg b/script_support/MPFS_ICICLE_MSS_linux.cfg
@@ -1016,7 +1016,7 @@ LPDDR4_TIMING_RAS                                   42
 LPDDR4_TIMING_RC                                    63
 LPDDR4_TIMING_RCD                                   18
 LPDDR4_TIMING_REFI                                  3.905
-LPDDR4_TIMING_RFC                                   380
+LPDDR4_TIMING_RFC                                   280
 LPDDR4_TIMING_RP                                    21
 LPDDR4_TIMING_RRD                                   10
 LPDDR4_TIMING_RTP                                   10