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Updated links to the PolarFire SoC GitHub with redirect links
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@hughbreslin
hughbreslin committed Oct 3, 2022
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This repository can be used to generate a reference design for the PolarFire SoC Icicle Kit. This reference design will have the same or extended functionality compared to the pre-programmed FPGA design on the Icicle Kit.

A Libero SoC Tcl script is provided to generate the reference design using Libero SoC along with device specific I/O constraints. For Tcl scripts supporting previous versions of Libero SoC see [Releases](https://github.com/polarfire-soc/icicle-kit-reference-design/releases).
A Libero SoC Tcl script is provided to generate the reference design using Libero SoC along with device specific I/O constraints. For Tcl scripts supporting previous versions of Libero SoC see [Releases](https://mi-v-ecosystem.github.io/redirects/releases-icicle-kit-reference-design).

This repository supports Libero SoC v2022.2 and above, which is available for download [here](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#Documents%20and%20Downloads). The release notes will note the version(s) of Libero that these scripts have been tested on.

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| :------------- | :------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
| DRI_CCC_DEMO | Instantiates a Clock Conditioning Circuitry core in the fabric and connects it to the Dynamic Reconfiguration Interface used with the PCIe. The outputs of the CCC are connected to I/Os which can be monitored using a logic analyzer. The clocks generated by the CCC can be controlled by the MSS using the DRI core. |
| I2C_LOOPBACK | Routes I2C0 and I2C1 to the fabric and connects them to bibufs routed to Raspberry Pi® I/Os. <br>Associates I2C loopback constraints for I/O. <br>This design can be used with the I2C loopback bare metal example project and will still boot Linux but the PAC1934 will be inaccessible. <br>I2C0_SCL is routed to pin 29 and I2C1_SCL is routed to pin 31 of the Raspberry Pi I/O header. <br>I2C0_SDA is routed to pin 35 and I2C1_SDA is routed to pin 37 of the Raspberry Pi I/O header. <br>Connecting / closing pins 29 and 31 and pins 35 and 37 of the Raspberry Pi I/O header will achieve I2C loopback. |
| SPI_LOOPBACK | Routes SPI0 to the fabric and connects the I/Os to the RPI header. Routes SPI1 to MSS I/Os on the MikroBUS header. <br>Associates SPI loopback constraints for I/O. <br>This design can be used with the [mpfs-spi-master-slave](https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples/tree/main/driver-examples/mss/mss-spi/mpfs-spi-master-slave) bare metal example project and will still boot Linux but QSPI will no longer work. <br>SPI0_MOSI is routed to pin 19 of the RPI header, SPI0_MISO is routed to pin 21 of the RPI header, SPI0_CLK is routed to pin 23 of the RPI header and SPI0_SS is routed to pin 24 of the RPI header. <br>To run the demo: <br> - connect MOSI (pin 6) of the mikroBUS header to SPI0_MOSI (pin 19) of the RPI header <br> - connect MISO (pin 5) of the mikroBUS header to SPI0_MISO (pin 21) of the RPI header <br> - connect SCK (pin 4) of the mikroBUS header to SPI0_CLK (pin 23) of the RPI header <br> - connect CS (pin 3) of the mikroBUS header to SPI0_SS (pin 24) of the RPI header. |
| SPI_LOOPBACK | Routes SPI0 to the fabric and connects the I/Os to the RPI header. Routes SPI1 to MSS I/Os on the MikroBUS header. <br>Associates SPI loopback constraints for I/O. <br>This design can be used with the driver-examples/mss/mss-spi/mpfs-spi-master-slave example from the [bare metal examples](https://mi-v-ecosystem.github.io/redirects/repo-polarfire-soc-bare-metal-examples) repository. This example project and will still boot Linux but QSPI will no longer work. <br>SPI0_MOSI is routed to pin 19 of the RPI header, SPI0_MISO is routed to pin 21 of the RPI header, SPI0_CLK is routed to pin 23 of the RPI header and SPI0_SS is routed to pin 24 of the RPI header. <br>To run the demo: <br> - connect MOSI (pin 6) of the mikroBUS header to SPI0_MOSI (pin 19) of the RPI header <br> - connect MISO (pin 5) of the mikroBUS header to SPI0_MISO (pin 21) of the RPI header <br> - connect SCK (pin 4) of the mikroBUS header to SPI0_CLK (pin 23) of the RPI header <br> - connect CS (pin 3) of the mikroBUS header to SPI0_SS (pin 24) of the RPI header. |
| BFM_SIMULATION | Generates a smart design test bench based on the reference design and imports custom BFM scripts to generate transactions on MSS FICs. <br>A custom DO file is also imported to add waves and run the simulation |
| MSS_BAREMETAL | This argument generates an MSS configuration which supports the bare metal projects supplied in the bare metal examples repository. The MSS configuration has no additional functionality, in this case the majority of DDR is available in the 1GB address space. |
| MSS_LINUX | This argument generates an MSS configuration which supports PolarFire SoC Linux builds. The MSS configuration has no additional functionality, in this case the majority of DDR is available in the 64GB address space. This configuration is generated by default. |
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| PROGRAM | Runs the full design flow after generating a design and programs a connected device. <br>Note: the device must be connected when the "Run PROGRAM Action" stage of the design flow is reached and only one device should be connected |
| EXPORT_FPE | Runs the full design flow after generating a design and exports a FlashPro Express file to the local directory |
| EXPORT_FPE:PATH | Runs the full design flow after generating a design and exports a FlashPro Express file to a specified path e.g EXPORT_FPE:/home/user/jobs/ |
| AXI4_STREAM_DEMO | Demonstrates configuring and implementing an AXI4 streaming interface on an CoreAXI4DMAController.<br> Creates the AXI4_STREAM_DATA_GENERATOR module which connects to the CoreAXI4DMAController in the design. The AXI4_STREAM_DATA_GENERATOR module generates AXI4 Stream transactions with incrementing data which can be used to benchmark the performance of the system. Further information regarding this demonstration is available in the following [guide](https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/demo-guides/mpfs-axi4-stream-demo.md). |
| AXI4_STREAM_DEMO | Demonstrates configuring and implementing an AXI4 streaming interface on an CoreAXI4DMAController.<br> Creates the AXI4_STREAM_DATA_GENERATOR module which connects to the CoreAXI4DMAController in the design. The AXI4_STREAM_DATA_GENERATOR module generates AXI4 Stream transactions with incrementing data which can be used to benchmark the performance of the system. Further information regarding this demonstration is available in the following [guide](https://mi-v-ecosystem.github.io/redirects/demo-guides_mpfs-axi4-stream-demo). |

**Note:** The arguments listed in the table above can be used with other arguments - i.e you can pass "I2C_LOOPBACK", "HSS_UPDATE" and "PROGRAM" as arguments.

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<a name="board-configuration"></a>
## Board configuration

For Icicle Kit jumper configurations used by this design and Linux images for eMMC and SD Cards see: [Updating PolarFire SoC Icicle-Kit FPGA Design and Linux Image](https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md).
For Icicle Kit jumper configurations used by this design and Linux images for eMMC and SD Cards see the [MPFS Icicle Kit User Guide](https://mi-v-ecosystem.github.io/redirects/updating-icicle-kit_updating-icicle-kit-design-and-linux).

<a name="mss-configuration"></a>
## MSS Configuration
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