Arg designs: Update project names

Updated the BFM_SIMULATION and AXI4_STREAM_DEMO arguments to generate independant project names from the base and also when used in conjunction.
polarfire-soc · Oct 18, 2022 · 8af0ec5 · 8af0ec5
1 parent 041bc00
commit 8af0ec5
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Showing 4 changed files with 14 additions and 2 deletions.
diff --git a/.gitignore b/.gitignore
@@ -4,6 +4,9 @@ MPFS_ICICLE_SPI_LOOPBACK/
 MPFS_ICICLE_Vectorblox/
 MPFS_ICICLE_DRI_CCC_DEMO/
 MPFS_ICICLE_MICRON_QSPI/
+MPFS_ICICLE_AXI4_STREAM_DEMO/
+MPFS_ICICLE_AXI4_STREAM_DEMO_BFM/
+MPFS_ICICLE_BFM_SIMULATION/
 script_support/Unsupported_Cores_List.txt
 script_support/components/MSS/
 script_support/components/MSS_I2C_LOOPBACK/

diff --git a/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl b/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl
@@ -60,6 +60,15 @@ if {[info exists I2C_LOOPBACK]} {
 } elseif {[info exists MICRON_QSPI]} {
     set project_name "MPFS_ICICLE_MICRON_QSPI"
     set project_dir "$local_dir/MPFS_ICICLE_MICRON_QSPI"
+} elseif {[info exists BFM_SIMULATION] && [info exists AXI4_STREAM_DEMO]} {
+    set project_name "MPFS_ICICLE_AXI4_STREAM_DEMO_BFM"
+    set project_dir "$local_dir/MPFS_ICICLE_AXI4_STREAM_DEMO_BFM"
+} elseif {[info exists AXI4_STREAM_DEMO]} {
+    set project_name "MPFS_ICICLE_AXI4_STREAM_DEMO"
+    set project_dir "$local_dir/MPFS_ICICLE_AXI4_STREAM_DEMO"
+} elseif {[info exists BFM_SIMULATION]} {
+    set project_name "MPFS_ICICLE_BFM_SIMULATION"
+    set project_dir "$local_dir/MPFS_ICICLE_BFM_SIMULATION"
 } else {
     set project_name "MPFS_ICICLE"
     set project_dir "$local_dir/MPFS_ICICLE"

diff --git a/...pport/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl b/...pport/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl
@@ -26,7 +26,7 @@ generate_component -component_name {FIC_3_PERIPHERALS} -recursive 0
 sd_update_instance -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -instance_name {FIC_3_PERIPHERALS_1} 
 build_design_hierarchy 
 
-create_hdl_core -file {./MPFS_ICICLE/hdl/AXI4_STREAM_DATA_GENERATOR.v} -module {AXI4_STREAM_DATA_GENERATOR} -library {work} -package {} 
+create_hdl_core -file "${project_dir}/hdl/AXI4_STREAM_DATA_GENERATOR.v" -module {AXI4_STREAM_DATA_GENERATOR} -library {work} -package {} 
 
 #	adding the signal to the BIF	
 hdl_core_add_bif -hdl_core_name {AXI4_STREAM_DATA_GENERATOR} -bif_definition {APB:AMBA:AMBA2:slave} -bif_name {APB_TARGET} -signal_map {} 

diff --git a/...t/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl b/...t/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl
@@ -55,7 +55,7 @@ build_design_hierarchy
 #   creating a HDL core from the data generator
 # sd_instantiate_hdl_module -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -hdl_module_name {AXI4_STREAM_DATA_GENERATOR} -hdl_file {hdl\AXI4_STREAM_DATA_GENERATOR.v} -instance_name {} 
 build_design_hierarchy 
-create_hdl_core -file {./MPFS_ICICLE/hdl/AXI4_STREAM_DATA_GENERATOR.v} -module {AXI4_STREAM_DATA_GENERATOR} -library {work} -package {}
+create_hdl_core -file "${project_dir}/hdl/AXI4_STREAM_DATA_GENERATOR.v" -module {AXI4_STREAM_DATA_GENERATOR} -library {work} -package {}
 
 #   creating the APB BIF on the data generator
 hdl_core_add_bif -hdl_core_name {AXI4_STREAM_DATA_GENERATOR} -bif_definition {APB:AMBA:AMBA2:slave} -bif_name {APB_TARGET} -signal_map {}