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Updated AXI4 interconnect 1 slave1 to give full 64GB address region t…
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…o PCI

Updated AXI4 interconnect 0 slave 1 to give access to DDR cached address space
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@hughbreslin
hughbreslin committed Nov 10, 2020
1 parent 4aef117 commit ecf2db0
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions script_support/TCL_PARAMETERS_BASE_DESIGN.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -1439,7 +1439,7 @@ set SLAVE0_CHAN_RS_0 "SLAVE0_CHAN_RS:true"
set SLAVE0_CLOCK_DOMAIN_CROSSING_0 "SLAVE0_CLOCK_DOMAIN_CROSSING:false"
set SLAVE0_DATA_WIDTH_0 "SLAVE0_DATA_WIDTH:64"
set SLAVE0_DWC_DATA_FIFO_DEPTH_0 "SLAVE0_DWC_DATA_FIFO_DEPTH:16"
set SLAVE0_END_ADDR_0 "SLAVE0_END_ADDR:0x7fffffff"
set SLAVE0_END_ADDR_0 "SLAVE0_END_ADDR:0xbfffffff"
set SLAVE0_END_ADDR_UPPER_0 "SLAVE0_END_ADDR_UPPER:0x0"
set SLAVE0_READ_INTERLEAVE_0 "SLAVE0_READ_INTERLEAVE:false"
set SLAVE0_START_ADDR_0 "SLAVE0_START_ADDR:0x60000000"
Expand Down Expand Up @@ -2898,8 +2898,8 @@ set SLAVE0_CHAN_RS_1 "SLAVE0_CHAN_RS:true"
set SLAVE0_CLOCK_DOMAIN_CROSSING_1 "SLAVE0_CLOCK_DOMAIN_CROSSING:false"
set SLAVE0_DATA_WIDTH_1 "SLAVE0_DATA_WIDTH:64"
set SLAVE0_DWC_DATA_FIFO_DEPTH_1 "SLAVE0_DWC_DATA_FIFO_DEPTH:16"
set SLAVE0_END_ADDR_1 "SLAVE0_END_ADDR:0x7fffffff"
set SLAVE0_END_ADDR_UPPER_1 "SLAVE0_END_ADDR_UPPER:0x0"
set SLAVE0_END_ADDR_1 "SLAVE0_END_ADDR:0xffffffff"
set SLAVE0_END_ADDR_UPPER_1 "SLAVE0_END_ADDR_UPPER:0x2f"
set SLAVE0_READ_INTERLEAVE_1 "SLAVE0_READ_INTERLEAVE:false"
set SLAVE0_START_ADDR_1 "SLAVE0_START_ADDR:0x70000000"
set SLAVE0_START_ADDR_UPPER_1 "SLAVE0_START_ADDR_UPPER:0x0"
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